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AX88796 数据表(PDF) 46 Page - ASIX Electronics Corporation

部件名 AX88796
功能描述  3-in-1 Local Bus Fast Ethernet Controller
PDF  71 Pages
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制造商  ASIX [ASIX Electronics Corporation]
网页  http://www.asix.com.tw
标志 ASIX - ASIX Electronics Corporation

AX88796 数据表(HTML) 46 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
46
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
5.2.10 MR17 –Autonegotiation Register A Bit Descriptions
FIELD
TYPE
DESCRIPTION
17.15-13
R
Reserved. Always 0.
17.12
R
Next Page Wait.
17.11
R
Wait Link_Fail_Inhibit_Wait_Timer (Link Status Check).
17.10
R
Wait Autoneg_Wait_Timer (Link Status Check).
17.9
R
Wait Break_Link_Timer (Transmit Disable).
17.8
R
Parallel Detection Fault.
17.7
R
Autonegotiation Enable.
17.6
R
FLP Link Good Check.
17.5
R
Complete Acknowledge.
17.4
R
Acknowledge Detect.
17.3
R
FLP Link Good.
17.2
R
Link Status Check.
17.1
R
Ability Detect.
17.0
R
Transmit Disable.
5.2.11 MR18 –Autonegotiation Register B Bit Descriptions
FIELD
TYPE
DESCRIPTION
18.15
R
Receiving FLPs. Any of FLP Capture, Clock, Data_0, or Data_1 (FLP
Rcv).
18.14
R
FLP Pass (FLP Rcv).
18.13
R
Link Pulse Count (FLP Rcv).
18.12
R
Link Pulse Detect (FLP Rcv).
18.11
R
Test Pass (NLP Rcv).
18.10
R
Test Fail Count (NLP Rcv).
18.9
R
Test Fail Extend (NLP Rcv).
18.8
R
Wait Max Timer Ack (NLP Rcv).
18.7
R
Detect Freeze (NLP Rcv).
18.6
R
Test Fail (NLP Rcv).
18.5
R
Transmit Count Ack (FLP Xmit).
18.4
R
Transmit Data Bit (FLP Xmit).
18.3
R
Transmit Clock Bit (FLP Xmit).
18.2
R
Transmit ability (FLP Xmit).
18.1
R
Transmit Remaining Acknowledge (FLP Xmit).
18.0
R
Idle (FLP Xmit).
5.2.12 MR20 –User Defined Register Bit Descriptions
FIELD
TYPE
DESCRIPTION
20.[15:0]
R/W
The data written into this user-defined register appears on the
REG20_OUT[15:0] bus.



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