AX88796 datasheet(55/71 Pages) ASIX

55 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

7.4 A.C. Timing Characteristics

7.4.1 XTAL / CLOCK

LCLK/XTALIN

Tlow

CLKO

Tod

Symbol

Description

Min

Typ.

Max

Units

Tcyc

CYCLE TIME

Thigh

CLK HIGH TIME

Tlow

CLK LOW TIME

Tr/Tf

CLK SLEW RATE

Tod

LCLK/XTALIN TO CLKO OUT DELAY

7.4.2 Reset Timing

LCLK/XTALIN

RESET

/RESET

Symbol

Description

Min

Typ.

Max

Units

Trst

Reset pulse width

100

LClk

Warning: Some chips may needed long power down for successful PHY auto

negotiation

Root of cause:

The PHY inside of AX88796 has a special request due to the semiconductor’s process. Namely,

it needs a very long power down for successful Auto Negotiation for some chips. We made a test

in lab and found it would be no problem if the PHY's initial time kept for 2 sec for all chips. If the

power down is less then this number, some of the PHY's Auto Negotiation will not be complete

and there will be potential to cause the link fail. If the auto negotiation time is not long enough,

uncertain numbers of chip may not work properly.

Tcyc

Thigh

AX88796 数据表(PDF) 55 Page - ASIX Electronics Corporation

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