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AX88796 数据表(PDF) 42 Page - ASIX Electronics Corporation |
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AX88796 数据表(HTML) 42 Page - ASIX Electronics Corporation |
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42 / 71 page ![]() ASIX ELECTRONICS CORPORATION 42 AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 5.2.2 MR1 -- Status Register Bit Descriptions FIELD TYPE DESCRIPTION 1.15 (T4ABLE) R 100Base-T4 Ability. This bit will always be a 0. 0: Not able. 1: Able. 1.14 (TXFULDUP) R 100Base-TX Full-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.13 (TXHAFDUP) R 100Base-TX Half-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.12 (ENFULDUP) R 10Base-T Full-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.11 (ENHAFDUP) R 10Base-T Half-Duplex Ability. This bit will always be a 1. 0: Not able. 1: Able. 1.10:7 (RESERVED) R Reserved. All bits will read as a 0. 1.6 (NO_PA_OK) R Suppress Preamble. When this bit is set to a 1, it indicates that the PHY accepts management frames with the preamble suppressed. 1.5 (NWAYDONE) R Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation process has been completed. The contents of registers MR4, MR5, MR6, and MR7 are now valid. The default value is a 0. This bit is reset when autonegotiation is started. 1.4 (REM_FLT) R Remote Fault. When this bit is a 1, it indicates a remote fault has been detected. This bit will remain set until cleared by reading the register. The default is a 0. 1.3 (NWAYABLE) R Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform autonegotiation. The value of this bit is always a 1. 1.2 (LSTAT_OK) R Link Status. When this bit is a 1, it indicates a valid link has been established. This bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 1.1 (JABBER) R Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will remain set until it is read, and the jabber condition no longer exists. 1.0 (EXT_ABLE) R Extended Capability. This bit indicates that the PHY supports the extended register set (MR2 and beyond). It will always read a 1. |
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