AX88796 datasheet(20/71 Pages) ASIX

20 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

If address Y is found to hash to the value 32 (20H), then FB32 in MAR2 should be initialized to ``1''. This will cause the

AX88796 to accept any multicast packet with the address Y.

Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64

logical address filteres if these addresses are chosen to map into unique locations in the multicast filter.

Note: The first bit of received packet sequence is 1’s stands by Multicast Address.

4.1.3 Broadcast Address Match Filter

The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s, that is

the values are “FF FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the Protocol Control

Logic rejects the packet.

4.1.4 Aggregate Address Filter with Receive Configuration Setup

The final address filter decision depands on the destination address types, identified by the above 3 address

match filters, and the setup of parameters of Receive Configuration Register.

Definitions of address match filter result are as following:

Signal

Value

Description

Phy

Unicast Address Match

Unicast Address not Match

Mul

Multicast Address Match

Multicast Address not Match

Bro

Brocast Address Match

Brocast Address not Match

AGG

Aggregate Address Match

Aggregate Address not Match

The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register”

32-bit CRC Generator

Latch

1 of 64 bit decoder

Filter bit array

X=31 to X=26

Clock

Selected bit

0 = reject, 1= accept

AX88796 数据表(PDF) 20 Page - ASIX Electronics Corporation

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