AX88796 datasheet(2/71 Pages) ASIX

2 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

CONTENTS

1.0 INTRODUCTION .............................................................................................................................................. 5

1.1 GENERAL DESCRIPTION:..................................................................................................................................... 5

1.2 AX88796 BLOCK DIAGRAM: .............................................................................................................................. 5

1.3A AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6

1.3B AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION ........................................................................ 7

1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode ................................................................................ 8

1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode................................................................................... 9

1.3.3 AX88796 Pin Connection Diagram for MC68K Mode .............................................................................. 10

1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode ............................................................................. 11

2.0 SIGNAL DESCRIPTION ................................................................................................................................. 12

2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 12

2.2 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP ......................................................................................... 13

2.3 BUILT-IN PHY LED INDICATOR PINS GROUP ..................................................................................................... 13

2.4 EEPROM SIGNALS GROUP .............................................................................................................................. 14

2.5 MII INTERFACE SIGNALS GROUP(OPTIONAL) ..................................................................................................... 14

2.6 STANDARD PRINTER PORT (SPP) INTERFACE PINS GROUP (OPTIONAL)................................................................ 15

2.7 GENERAL PURPOSE I/O PINS GROUP........................................................................................... 15

2.8 MISCELLANEOUS PINS GROUP............................................................................................................................ 16

2.9 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE..................... 17

3.0 MEMORY AND I/O MAPPING...................................................................................................................... 18

3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 18

3.2 I/O MAPPING................................................................................................................................................... 18

3.3 SRAM MEMORY MAPPING .............................................................................................................................. 18

4.0 BASIC OPERATION ...................................................................................................................................... 19

4.1 RECEIVER FILTERING ....................................................................................................................................... 19

4.1.1 Unicast Address Match Filter................................................................................................................... 19

4.1.2 Multicast Address Match Filter ................................................................................................................ 19

4.1.3 Broadcast Address Match Filter............................................................................................................... 20

4.1.4 Aggregate Address Filter with Receive Configuration Setup..................................................................... 20

4.2 BUFFER MANAGEMENT OPERATION .................................................................................................................. 22

4.2.1 Packet Reception ..................................................................................................................................... 22

4.2.2 Packet Transmision .................................................................................................................................. 25

4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory) .................................................................... 27

4.2.4 Removing Packets from the Ring (Host read data from memory) .............................................................. 28

4.2.5 Other Useful Operations .......................................................................................................................... 31

5.0 REGISTERS OPERATION ............................................................................................................................. 32

5.1 MAC CORE REGISTERS.................................................................................................................................... 32

5.1.1 Command Register (CR) Offset 00H (Read/Write) ................................................................................... 34

5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write) .......................................................................... 34

5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 35

5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) .......................................................................... 35

5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 35

5.1.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 36

5.1.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 36

5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 36

5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 37

5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ................................................................. 37

5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ................................................................. 37

5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 37

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