AX88796 datasheet(53/71 Pages) ASIX

53 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

6.5 CPU Access MII Station Management functions.

Basic Operation

The primary function of station management is to transfer control and status information about the PHY to a

management entity. This function is accomplished by the MDC clock input from MAC entity, which has a

maximum frequency of 12.5 MHz (for internal PHY only, as to external PHY please refer to the relevant

specification), along with the MDIO signal.

The Internal PHY address is fixed to 10h and the equivalent circuit is shown as below:

A specific set of registers and their contents (described in Tab - 16 MII Management Frames- field Description)

defines the nature of the information transferred across the MDIO interface. Frames transmitted on the MII

management interface will have the frame structure shown in Tab - 15 MII Management Frame Format. The

order of bit transmission is from left to right. Note that reading and writing the management register must be

completed without interruption.

Read/Write

(R/W)

Pre

PHYAD

REGAD

DATA

IDLE

1. . .1

AAAAA

RRRRR

DDDDDDDDDDDDDDDD

1. . .1

AAAAA

RRRRR

DDDDDDDDDDDDDDDD

Tab - 15 MII Management Frame Format

Field

Descriptions

Pre

Preamble. The PHY will accept frames with no preamble. This is indicated by a 1 in register 1, bit 6.

Start of Frame. The start of frame is indicated by a 01 pattern.

Operation Code. The operation code for a read transaction is 10. The operation code for a write

transaction is a 01.

PHYADD

PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address

bit transmitted and received is the MSB of the address. A station management entity that is

attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for

each entity.

REGAD

first register address bit transmitted and received is the MSB of the address.

Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and

the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a

write to the PHY, these bits is driven to 10 by the station. During a read, the MDIO is not

driven during the first bit time and is driven to a 0 by the PHY during the second bit time.

DATA

Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register

being addressed.

IDLE

Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be

disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1.

Tab - 16 MII Management Frames- field Description

Y (MUX)

(Internal PHY)

MDC

MDIO-OUT

MDIO-IN

If (PHY_ID==10h) then S=1 else S=0

Pin67

MDC

Pin66

MDIO

From Register

Offset 14h

MDC

MDO

MDI

MDIR

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