AX88796 datasheet(41/71 Pages) ASIX

41 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.2.1 MR0 -- Control Register Bit Descriptions

FIELD

TYPE

DESCRIPTION

0.15 (SW_RESET)

R/W

Reset. Setting this bit to a 1 will reset the PHY. All registers will be set to

their default state. This bit is self-clearing. The default is 0.

0.14 (LOOPBACK)

R/W

Loopback. When this bit is set to 1, no data transmission will take place on

the media. Any receive data will be ignored. The loopback signal path will

contain all circuitry up to, but not including, the PMD. The default value is

a 0.

0.13(SPEED100)

R/W

Speed Selection. The value of this bit reflects the current speed of operation

(1 = 100Mbits/s; 0 = 10Mbits/s). This bit will only affect operating speed

when the autonegotiation enable bit (register 0, bit 12) is disabled (0). This

bit is ignored when autonegotiation is enabled (register 0, bit 12). This bit is

ANDed with the SPEED_PIN signal.

0.12 (NWAY_ENA)

R/W

Autonegotiation Enable. The autonegotiation process will be enabled by

set-ting this bit to a 1. The default state is a 1.

0.11 (PWRDN)

R/W

Powerdown. The PHY may be placed in a low-power state by setting this bit

to a 1, both the 10Mbits/s transceiver and the 100Mbits/s transceiver will be

powered down. While in the power down state, the PHY will respond to

management transactions. The default state is a 0.

0.10 (ISOLATE)

R/W

Isolate. When this bit is set to a 1, the MII outputs will be brought to the

high-impedance state. The default state is a 0.

0.9 (REDONWAY)

R/W

Restart Autonegotiation. Normally, the autonegotiation process is started

at powerup. The process may be restarted by setting this bit to a 1. The

default state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this

bit goes to a 1. This bit is self-cleared when autonegotiation restarts.

0.8 (FULL_DUP)

R/W

Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 =

half duplex). This bit is ignored when the autonegotiation enable bit

(register 0, bit 12) is enabled. The default state is a 0. This bit is ORed with

the F_DUP pin.

0.7 (COLTST)

R/W

Collision Test. When this bit is set to a 1, the PHY will assert the MCOL

signal in response to MTX_EN.

0.6:0 (RESERVED)

Reserved. All bits will read 0.

AX88796 数据表(PDF) 41 Page - ASIX Electronics Corporation

AX88796 数据表(HTML) 41 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

数据表下载