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AX88796 数据表(PDF) 32 Page - ASIX Electronics Corporation |
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AX88796 数据表(HTML) 32 Page - ASIX Electronics Corporation |
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32 / 71 page  ASIX ELECTRONICS CORPORATION 32 AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 5.0 Registers Operation 5.1 MAC Core Registers All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS (Page Select) in the Command Register. PAGE 0 (PS1=0,PS0=0) OFFSET READ WRITE 00H Command Register ( CR ) Command Register ( CR ) 01H Page Start Register ( PSTART ) Page Start Register ( PSTART ) 02H Page Stop Register ( PSTOP ) Page Stop Register ( PSTOP ) 03H Boundary Pointer ( BNRY ) Boundary Pointer ( BNRY ) 04H Transmit Status Register ( TSR ) Transmit Page Start Address ( TPSR ) 05H Number of Collisions Register ( NCR ) Transmit Byte Count Register 0 ( TBCR0 ) 06H Current Page Register ( CPR ) Transmit Byte Count Register 1 ( TBCR1 ) 07H Interrupt Status Register ( ISR ) Interrupt Status Register ( ISR ) 08H Current Remote DMA Address 0 ( CRDA0 ) Remote Start Address Register 0 ( RSAR0 ) 09H Current Remote DMA Address 1 ( CRDA1 ) Remote Start Address Register 1 ( RSAR1 ) 0AH Reserved Remote Byte Count 0 ( RBCR0 ) 0BH Reserved Remote Byte Count 1 ( RBCR1 ) 0CH Receive Status Register ( RSR ) Receive Configuration Register ( RCR ) 0DH Reserved Transmit Configuration Register ( TCR ) 0EH Reserved Data Configuration Register ( DCR ) 0FH Reserved Interrupt Mask Register ( IMR ) 10H, 11H Data Port Data Port 12H IFGS1 IFGS1 13H IFGS2 IFGS2 14H MII/EEPROM Access MII/EEPROM Access 15H Test Register Test Register 16H Inter-frame Gap (IFG) Inter-frame Gap (IFG) 17H GPI GPOC 18H - 1AH Standard Printer Port (SPP) Standard Printer Port (SPP) 1BH - 1EH Reserved Reserved 1FH Reset Reserved Tab - 12 Page 0 of MAC Core Registers Mapping |
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