AX88796 datasheet(22/71 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

4.2 Buffer Management Operation

There are four buffer memory access types used in AX88796.

1. Packet Reception (Write data to memory from MAC)

2. Packet Transmision (Read data from memory to MAC)

3. Filling Packets to Transmit Buffer (Host fill data to memory)

4. Removing Packets from the Receive Buffer Ring (Host read data from memory)

The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local

DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write

operation and type 4 does Remote DMA read operation.

4.2.1 Packet Reception

The Local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length

256 byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is

programmed in two registers, a Page Start and a Page Stop Register. Ethernet packets consist of minimum

packet size (64 bytes) to maximum packet size (1522 bytes), the 256 byte buffer length provides a good

compromise between short packets and longer packets to most efficiently use memory. In addition these buffers

provide memory resources for storage of back-to-back packets in loaded networks. The assignment of buffers

for storing packets is controlled by Buffer Management Logic in the AX88796. The Buffer Management Logic

provides three basic functions: linking receive buffers for long packets, recovery of buffers when a packet is

rejected, and recirculation of buffer pages that have been read by the host.

At initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring.

Two eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register

(PSTOP) define the physical boundaries of where the buffers reside. The AX88796 treats the list of buffers as a

logical ring; whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start

Address.

Buffer #1

Buffer #2

Buffer #3

…

Buffer #n

Physical Memory Map

Logic Receive Buffer Ring

Fig - 8 Receive Buffer Ring

4000h

8000h

Page Start

Page Stop

…

n-2

n-1

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