AX88796 datasheet(48/71 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.2.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions

FIELD

TYPE

DESCRIPTION

29.15 (LOCALRST)

R/W

Management Reset. This is the local management reset bit. Writing logic 1

to this bit will cause the lower 16 registers and registers 28 and 29 to be reset

to their default values. This bit is self-clearing.

29.14 (RST1)

R/W

Generic Reset 1. This register is used for manufacture test only.

29.13 (RST2)

R/W

Generic Reset 2. This register is used for manufacture test only.

29.12 (100_OFF)

R/W

100Mbits/s Transmitter Off. When this bit is set to 0, it forces TPI low and

TPIN- high. This bit defaults to 1.

29.11 (LED_BLINK)

R/W

LED Blinking. This register, when 1, enables LED blinking. This is ORed

with LED_BLINK_EN. Default is 0.

29.10 (CRS_SEL)

R/W

Carrier Sense Select. MCRS will be asserted on receive only when this bit

is set to a 1. If this bit is set to logic 0, MCRS will by asserted on receive or

transmit. This bit is ORed with the CRS_SEL pin.

29.9 (LINK_ERR)

R/W

Link Error Indication. When this bit is a 1, a link error code will be

reported on MRXD[3:0] of the PHY when MRX_ER is asserted on the MII.

The specific error codes are listed in the MRXD pin description. If it is 0, it

will disable this function.

29.8 (PKT_ERR)

R/W

Packet Error Indication Enable. When this bit is a 1, a packet error code,

which indicates that the scrambler is not locked, will be reported on

MRXD[3:0] of the PHY when MRX_ER is asserted on the MII. When this

bit is 0, it will disable this function.

29.7 (PULSE_STR)

R/W

Pulse Stretching. When this bit is set to 1, the CS, XS, and RS output

signals will be stretched between approximately 42 ms - 84 ms. If this bit is

0, it will disable this feature. Default state is 0.

29.6 (EDB)

R/W

Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B-encoder and

5B/4B-decoder function will be disabled. This bit is ORed with the EDBT

pin.

29.5 (SAB)

R/W

Symbol Aligner Bypass. When this bit is set to 1, the aligner function will

be disabled.

29.4 (SDB)

R/W

Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/

descrambling functions will be disabled. This bit is ORed with the SDBT

pin.

29.3 (CARIN_EN)

R/W

Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is

enabled. This bit is ORed with the CARIN_EN pin.

29.2 (JAM_COL)

R/W

Jam Enable. When this bit is a 1, it enables JAM associated with carrier

integrity to be ORed with MCOLMCRS.

29.1 (FEF-EN)

R/W

Far-End Fault Enable. This bit is used to enable the far-end fault detection

and transmission capability. This capability may only be used if

autonegotiation is disabled. This capability is to be used only with media

which does not support autonegotiation. Setting this bit to 1 enables far-end

fault detection, and logic 0 will disable the function. Default state is 0.

29.0 (FX)

R/W

Fiber-Optic Mode. When this bit is a 1, the PHY is in fiber-optic mode.

This bit is ORed with FX_MODE.

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