PCF8833USLASH2DA datasheet(43/112 Pages) PHILIPS

43 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

6.2.27

MEMORY DATA ACCESS CONTROL

The display data RAM access conditions can be defined by using the Memory data access control (MADCTL) command.

The used single control bits together with their reset states are given in Table 41.

Table 40 Memory data access control register bits

Note

1. Refer to Section 6.2.24.4 for an explanation of LAO on scroll modes and to Section 6.2.23 for an explanation of LAO

on Partial mode.

Table 41 Explanation of the memory data access control bits

The relationship between RAM and display for the MX, MY, RGB and LAO control bits is illustrated Fig.22.

Combinations of MX, MY and V are described in more detail in Section 7.2.

D/C

76543210

DEFAULT

000110110

36H

LAO(1)

RGB

00H

BIT

LOGIC 0 (RESET STATE)

LOGIC 1

no mirror Y

mirror Y

no mirror X

mirror X

RAM write in X direction

vertical RAM write; in Y direction

LAO

line address order (top to bottom)

line address order (bottom to top)

RGB

BGR

handbook, full pagewidth

MGU931

D7 = 1

D7 = 0

131

D6 = 0

D6 = 1

131

012

column address

RAM

0,0

131

D3 = 1:BGR

D3 = 0:RGB

column drivers

D4 = 1

D4 = 0

131

DISPLAY

interface

Fig.22 Display data RAM access control.

PCF8833U/2DA 数据表(PDF) 43 Page - NXP Semiconductors

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