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PCF8833U/2DA 数据表(PDF) 77 Page - NXP Semiconductors |
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PCF8833U/2DA 数据表(HTML) 77 Page - NXP Semiconductors |
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77 / 112 page  2003 Feb 14 77 Philips Semiconductors Objective specification STN RGB - 132 × 132 × 3 driver PCF8833 13 AC CHARACTERISTICS VDD1 = 1.5 to 3.3 V; VDD2 =VDD3 = 2.4 to 3.5 V; VSS1 =VSS2 =0V; Tamb = −40 to +85 °C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fframe LCD frame frequency (internal clock) VDD1 = 3.0 V − tbf − Hz fosc oscillator frequency notes 2 and 3 − 600 − kHz fclk(ext) external clock frequency − tbf − kHz Reset; see Fig.50 tW(RESL) reset LOW pulse width note 4 500 −− ns tRSS reset spike suppression −− 100 ns tSU;RESL reset LOW pulse set-up time after power-on 0 − 1 µs tRT initialization note 5 0 − 5ms tRI interface ready after reset pulse 0 − 1 µs Serial interface; VDD1(min) = 1.65 V; note 6; see Fig.51 TSCYC serial clock SCLK period (SCLK) 150 −− ns tSHW SCLK pulse width HIGH 60 −− ns tSLW SCLK pulse width LOW 60 −− ns tSDS SDIN data set-up time 60 −− ns tSDH SDIN data hold time 60 −− ns tACC SDOUT access time CL =30pF 10 − 50 ns tOH SDOUT output disable time CL = 5 pF; R=3k Ω 25 − 50 ns tSCC SCLK to SCE time 20 −− ns tCHW SCE pulse width HIGH 40 −− ns tCSS SCE to SCLK set-up time 60 −− ns tCSH SCE to SCLK hold time 65 −− ns 8-bit parallel (8080-type) interface; VDD1(min) = 1.65 V; note 6; see Fig.52 tCS CS-WR and CS-RD time note 7 10 −− ns tAH D/C address hold time 10 −− ns tAS address set-up time 10 −− ns TCYC system cycle time 160 −− ns tCCLW WR control pulse width LOW Write mode 38 −− ns tCCLR RD control pulse width LOW Read mode 38 −− ns tCCHW WR control pulse width HIGH Write mode 90 −− ns tCCHR RD control pulse width HIGH Read mode 90 −− ns tDS D0 to D7 data set-up time 10 −− ns tDH D0 to D7 data hold time 10 −− ns tACC read access time note 8; CL =30pF −− 30 ns tOH output disable time note 8; CL = 5 pF; R=3k Ω; note 9 30 − 160 ns |
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