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PCF8833U/2DA 数据表(PDF) 27 Page - NXP Semiconductors |
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PCF8833U/2DA 数据表(HTML) 27 Page - NXP Semiconductors |
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27 / 112 page  2003 Feb 14 27 Philips Semiconductors Objective specification STN RGB - 132 × 132 × 3 driver PCF8833 6.2.19 COLUMN ADDRESS SET The display data RAM parameters xs and xe define the column address range of the display data RAM for writing data. Parameters xs and xe are defined between 0 and 131 (83H), and xs must be smaller then xe. Table 29 Column address set register bits 6.2.20 PAGE ADDRESS SET The display data RAM parameters ys[7:0] and ye[7:0] define the page (row) address range of the display data RAM for writing data. Parameters ys and ye are defined between 0 and 131 (83H), and ys must be smaller then ye. Table 30 Page address set register bits 6.2.21 MEMORY WRITE Data written to the display memory (RAM) is validated by the Memory write (RAMWR) command. Entering this command always returns the page address and column address to the start addresses xs[7:0] and ys[7:0] respectively. Content of the display data RAM is written by the data entered following this command, with the page and/or column address automatically incremented. The data Write mode turned on by this command can be automatically cancelled by entering another command. After a power-up the display RAM content is undefined. Neither a hardware reset nor a software reset changes the data stored in display RAM. Sending display data must stop 160 ns before issuing a hardware reset, otherwise the last word written to the display RAM may be corrupted. Table 31 Memory write register bits D/C 76543210 DEFAULT 000101010 2AH 1 xs[7] xs[6] xs[5] xs[4] xs[3] xs[3] xs[3] xs[0] 02H 1 xe[7] xe[6] xe[5] xe[4] xe[3] xe[2] xe[1] xe[0] 81H D/C 76543210 DEFAULT 000111011 2BH 1 ys[7] ys[6] ys[5] ys[4] ys[3] ys[3] ys[3] ys[0] 02H 1 ye[7] ye[6] ye[5] ye[4] ye[3] ye[2] ye[1] ye[0] 81H D/C 76543210 DEFAULT 000101101 2CH 1 D7D6D5D4D3D2D1D0 XX |
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