PCF8833USLASH2DA datasheet(5/112 Pages) PHILIPS

5 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

PINNING

SYMBOL

PAD

TYPE

DESCRIPTION

R95 to R64

2 to 33

LCD row driver outputs

C0 to C395

34 to 429

LCD column driver outputs

R0 to R31

430 to 461

LCD row driver outputs

R63 to R32

464 to 495

LCD row driver outputs

RES

496

external reset; this signal will reset the device and must be applied to properly

initialize the chip (active LOW)

497

O/I

tearing line (in Normal mode it is always an output)

VSS1

498 to 507

system ground

VSS2

508 to 517

system ground

CS/SCE

518

chip select parallel interface or serial chip enable (active LOW)

VDD1

519 to 524

logic supply voltage

VDD3

525 to 529

VDD2 and VDD3 are the supply voltage pins for the internal voltage generator

including the temperature compensation circuits; VDD2 and VDD3 can be

connected together but in this case care must be taken to respect the supply

voltage range (see Chapter 13); VDD1 is used as the supply for the rest of the

chip. VDD1 can be connected together with VDD2 and VDD3 but in this case care

must also be taken to respect the supply voltage range; see Chapter 13. VDD2

and VDD3 must not be applied before VDD1.

If the internal voltage generator is not used, pins VDD2 and VDD3 must be

connected to VDD1.

VDD2

530 to 539

540

I/O