PCF8833USLASH2DA datasheet(58/112 Pages) PHILIPS

58 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

Table 70 Bias system ratios

Notes

1. For Partial mode internally P = 1 is set, otherwise P = 4 is selected. Limitations for Partial mode given in

Section 6.2.43.2 for respectively for full Display mode given in Section 6.2.43.1 have to be taken into account.

2. Reset state.

Table 71 Set bias system register bits; note 1

Note

1. X = don’t care.

VB[3:0]

F/Gmax

P=1(N=32)(1)

P=4(N= 132)(1)

0000

1.000

0.00

not allowed

0001

1.250

0.50

0010

1.375

0.75

0011

1.500

1.00

1.500

0100

1.625

1.25

1.625

0101

1.750

1.50

1.750

0110

1.875

1.75

1.875

0111

2.000

2.00

2.000

8.0

1000

2.125

2.25

2.125

8.5

1001

2.250

2.50

2.250

9.0

1010

2.375

2.75

2.375

9.5

1011

2.500

3.00

2.500

10.0(2)

1100

2.625

3.25

2.625

not allowed

1101

2.750

3.50

2.750

1110

2.875

3.75

2.875

1111

3.000

4.00

3.000

D/C

76543210

DEFAULT

011000111

C7H

XXXX

VB3

VB2

VB1

VB0

0BH

6.2.43.1

Limitations on bias voltages in Normal mode

VDD1: 1.5 to 3.3 V

VLCD1: 5.5 to 11 V

VLCD2: 10 to 20 V

(VLCD2 − VLCD1): 4.5 to 9 V

but for VLCD2: 10 to 11 V:

6.2.43.2

Limitations on bias voltages in Partial mode

VDD1: 1.5 to 3.3 V

VLCD1: 2.9 to 12 V

VLCD2: 3.8 to 12 V

LCD2

----------------

LVD1

–





0 to 1 V

LCD2

----------------

LCD1

–





0 to 0.5 V

LCD2

LCD1

–

()

max

0.5 V

PCF8833U/2DA 数据表(PDF) 58 Page - NXP Semiconductors

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