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PCF8833U/2DA 数据表(PDF) 82 Page - NXP Semiconductors |
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PCF8833U/2DA 数据表(HTML) 82 Page - NXP Semiconductors |
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82 / 112 page  2003 Feb 14 82 Philips Semiconductors Objective specification STN RGB - 132 × 132 × 3 driver PCF8833 15 MODULE MAKER PROGRAMMING The One Time Programmable (OTP) technology has been implemented in the PCF8833. It enables the module maker to perform an LCD supply voltage calibration after it has been assembled on an LCD module. The module maker can also pre-define command set registers in order to provide the setmaker with a ‘plug and play’ module where only display related data has to be sent. The PCF8833 features the following module maker programming facilities: • VLCD calibration • Multiplication factor S[1:0] to FS[1:0] for full Display mode and PS[1:0]) for partial Display mode • Set VPR[8:0] to FVPR[8:0] for full Display mode and PVPR[8:0] for partial Display mode • Set bias system VB[3:0] to FVB[3:0] for full Display mode and PVB[3:0] for partial Display mode • Segmented temperature compensation slopes for VLCD, SLA [2:0], SLB[2:0], SLC[2:0] and SLD[2:0] • Segmented temperature frame frequencies DFA[6:0], DFB[6:0], DFC[6:0] and DFD[6:0] • Frame frequency 8-colour mode DF8[6:0] • Identification bits ID2[7:0] and ID3[7:0] • TRS and BRS • Factory default bit EFD • Seal bit. 15.1 VLCD calibration The first feature included is the ability to adjust the VLCD voltage with a 6-bit code (MMVOPCAL). This code is implemented in twos complement notation giving rise to a positive or negative offset to the VPR register. The adder in the circuit has underflow and overflow protection. In the event of an overflow, the output will be clamped to VOP = 445; during an underflow the output will be clamped to 0. Figure 55 illustrates how the high voltage generator setting VOP is controlled. Compared to equation (1) in Section 6.2.31, Fig.55 also takes the temperature compensation VT into account (see Section 6.2.40), which is reflected in the following equation: VLCD =a+(VT[7:0] + MMVOPCAL[5:0] + VCON[6:0] + VPR[8:0]) × b handbook, full pagewidth MGU971 Temperature compensation VT, 8-bit value VT[7:0] VOP range −128 to +127 range −64 to +63 range −32 to +31 range 0 to 445 usable range 5 to 410 range 0 to 445 to high voltage generator OTP VLCD calibration, 6-bit offset MMVOPCAL[5:0] VPR register, 9-bit value VCON register, 7-bit VPR[8:0] + VCON[6:0] Fig.55 VLCD calibration. |
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