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PCF8833U/2DA 数据表(PDF) 29 Page - NXP Semiconductors

部件名 PCF8833U/2DA
功能描述  STN RGB - 132 X 132 X 3 driver
PDF  112 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCF8833U/2DA 数据表(HTML) 29 Page - NXP Semiconductors

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2003 Feb 14
29
Philips Semiconductors
Objective specification
STN RGB - 132
× 132 × 3 driver
PCF8833
The following steps must be followed to enter the Partial
mode:
• Set VOP (when the MMOTP cells are used the VOP for
the Partial mode is predefined)
• Set bias system (when the MMOTP cells are used the
bias system for the Partial mode is predefined)
• Set start address of active area AA1S[7:0]; can be set in
multiples of 4
• Set end address of active area AA1E[7:0] + 1; can be
set in multiples of 4
• Enter Partial mode (PTLON).
When setting the addresses the following conditions must
be ensured:
• (AA1E + 1) − AA1S = 32 (only 1 partial display size
setting is possible)
• AA1 ≥ 0 and AA1E ≤ 131.
Figure 8 shows how to use the Partial mode with Line
Address Order (LAO) set to logic 0. Figure 9 gives an
example of Partial mode with LAO set to logic 1, and
Fig.10 shows the position of the partial area when the start
address of the active area is AA1S
≥ (131 + 1) − 31, i.e.
AA1S
≥ 101 (AA1S must be set in multiples of 4).
Figure 11 shows how the Partial mode can be used.
MGU917
handbook, full pagewidth
0
1
2
3
4
5
6
7
8
9
10
11
12
13
42
127
128
129
130
131
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
ROW 3
ROW 1
ROW 0
ROW 2
ROW 7
ROW 5
ROW 4
ROW 6
ROW 11
ROW 9
ROW 8
ROW 10
ROW 13
ROW 12
ROW 31
ROW 29
ROW 28
ROW 30
ROW 35
ROW 33
ROW 32
ROW 34
ROW 39
ROW 37
ROW 36
ROW 38
ROW 41
ROW 40
ROW 42
ROW 27
ROW 25
ROW 24
ROW 26
ROW 129
ROW 127
ROW 128
ROW 131
ROW 130
AA1S [7:0] = 4
AA1E [7:0] +1 = 36
RAM
display
partial area
partial area
32
rows
Fig.8 Partial Display mode for LAO = 0.



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