PCF8833USLASH2DA datasheet(55/112 Pages) PHILIPS

55 / 112 page

2003 Feb 14

Philips Semiconductors

Objective speciﬁcation

STN RGB - 132

× 132 × 3 driver

PCF8833

Table 67 Offset value

TEMPERATURE RANGE

TD EQUIVALENT

OFFSET EQUATION VT

−40 °C0

× (MB + MA)

−40 °C to < −10 °C

0 to 31

(32

× MB)+MA × (32 − TD)

−10 to < 20 °C

32 to 63

(64

− TD) × MB

°Cto<50 °C64 to 95

−(TD − 64) × MC

50 to < 80

°C

96 to 127

−((32 × MC) + MD × (TD − 96))

≥80 °C

>127

−(32 × MC + 31 × MD)

6.2.41

FRAME FREQUENCY PROGRAMMING

The PCF8833 incorporates temperature segmented

Frame frequency programming (TCDF). The temperature

range is split into 4 areas as shown in Fig.31.

In each of the segments a Division Factor (DF) can be

programmed which determines the Frame Frequency

(FF). In equation (2) the frame frequency can be

calculated from a given division factor.

(2)

Where fosc is the oscillator frequency which is defined in

Chapter 13.

The Divider Factor (DF) is a 7-bit number so the upper

programming range is limited to 127DEC resulting in a

minimum frame frequency of 35.8 Hz. The lower

programming range is limited to 20DEC resulting in a

maximum frame frequency of 227 Hz. The frame

frequency is derived from the built-in oscillator, and thus

the tolerance of the frame frequency has the same ratio as

that given for the oscillator frequency; see Chapter 13.

When Partial mode is selected (see Sections 6.2.10 and

6.2.23) the same segmented frame frequencies will be

used as for the full Display mode.

132

----------

osc

--------------------------

Table 68 Frame frequency programming register bits; note 1

Note

1. X = don’t care.

D/C

76543210

DEFAULT

011000101

C5H

DFA6

DFA5

DFA4

DFA3

DFA2

DFA1

DFA0

38H

DFB6

DFB5

DFB4

DFB3

DFB2

DFB1

DFB0

35H

DFC6

DFC5

DFC4

DFC3

DFC2

DFC1

DFC0

30H

DFD6

DFD5

DFD4

DFD3

DFD2

DFD1

DFD0

25H

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