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HMC1197LP7FE 数据表(PDF) 29 Page - Analog Devices |
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HMC1197LP7FE 数据表(HTML) 29 Page - Analog Devices |
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29 / 57 page ![]() For price, delivery, and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC1197LP7FE v03.0314 Wideband direct Quadrature Modulator w/ Fractional-n Pll & Vco, 100 - 4000 MHz 29 Reg 04h = round(0.1 x 224) = round(1677721.6) = 1677722 fVCO = (56 + ) = 2805 MHz + 1.192 Hz error 1677722 224 50e6 1 (EQ 14) fout = = 1402.5 MHz + 0.596 Hz error fVCO 2 (EQ 15) In this example the output frequency of 1402.5 MHz is achieved by programming the 19-bit binary value of 56d = 38h into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah into frac_reg in Reg 04h. The 0.596 Hz quantization error can be eliminated using the exact frequency mode if required. In this example the VCO output fundamental 2805 MHz is divided by 2 (Reg 16h[5:0] = 2h) = 1402.5 MHz. 1.3.7.5 exact Frequency tuning Due to quantization effects, the absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fractional modulator. For example, a 24 bit fractional modulator has frequency resolution set by the phase detector (PD ) comparison rate divided by 224. The value 224 in the denominator is sometimes referred to as the modulus. Hittite PLLs use a fixed modulus which is a binary number. In some types of fractional PLLs the modulus is variable, which allows exact frequency steps to be achieved with decimal step sizes. Unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period (channel step size). For this reason Hittite PLLs use a large fixed modulus. Normally, the step size is set by the size of the fixed modulus. In the case of a 50 MHz PD rate, a modulus of 224 would result in a 2.98 Hz step resolution, or 0.0596 ppm. In some applications it is necessary to have exact frequency steps, and even an error of 3 Hz cannot be tolerated. Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be exactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common frequencies cannot be exactly represented. For example, Nfrac = 0.1 = 1/10 must be approximated as round((0.1 x 224)/ 224 ) ≈ 0.100000024. At fPD = 50 MHz this translates to 1.2 Hz error. Hittite’s exact frequency mode addresses this issue, and can eliminate quantization error by programming the channel step size to FPD/10 in Reg 0Ch to 10 (in this example). More generally, this feature can be used whenever the desired frequency, fVCO, can be exactly represented on a step plan where there are an integer number of steps (<224) across integer-N boundaries. Mathematically, this situation is satisfied if: = = ≥ gcd gcd gcd 1 24 mod 0 where gcd( , ) 2 PD PD VCOk VCO f f f f f f and f (EQ 16) Where: gcd stands for Greatest Common Divisor fN = maximum integer boundary frequency < fVCO1 fPD = frequency of the Phase Detector and fVCOk are the channel step frequencies where 0 < k < 224-1, As shown in Figure 40. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D |
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