HMC1197LP7FE datasheet(27/57 Pages) AD

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

1.3.5.3 configuring ld_Sdo Pin for ld output

Setting Reg 0Fh[4:0]=1 will display the Lock Detect Flag on LD_SDO pin of the HMC1197LP7FE. If locked,

LD_SDO will be high. As the name suggests, LD_SDO pin is multiplexed between LD and SDO (Serial

Data Out) signals. Hence LD is available on the LD_SDO pin at all times except when a serial port read

is requested, in which case the pin reverts temporarily to the Serial Data Out pin, and returns to the Lock

Detect Flag after the read is completed.

LD can be made available on LD_SDO pin at all times by writing Reg 0Fh[6] = 1. In that case the

HMC1197LP7FE will not provide any read-back functionality because the SDO signal is not available.

1.3.6

cycle Slip Prevention (cSP)

When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneous

frequencies of the two PD inputs are different, and the phase difference of the two inputs at the PD varies

rapidly over a range much greater than ±2π radians. Since the gain of the PD varies linearly with phase

up to ±2π, the gain of a conventional PD will cycle from high gain, when the phase difference approaches

a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. The

output current from the charge pump will cycle from maximum to minimum even though the VCO has not

yet reached its final frequency.

The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the

cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena is

known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically.

Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal

Laplace analysis.

The HMC1197LP7FE PD features an ability to reduce cycle slipping during frequency tunning. The Cycle

Slip Prevention (CSP) feature increases the PD gain during large phase errors.

1.3.7

Frequency tuning

HMC1197LP7FE VCO subsystem always operates in fundamental frequency of operation (2050 MHz to

4100 MHz). The HMC1197LP7FE generates frequencies below its fundamental frequency (33 MHz to 2050

MHz) by tuning to the appropriate fundamental frequency and selecting the appropriate Output Divider

setting (divide by 2/4/6.../60/62) in Reg 16h[5:0].

The HMC1197LP7FE automatically controls frequency tuning in the fundamental band of operation, for

more information see “1.2.1 VCO Calibration”.

To tune to frequencies below the fundamental frequency range (<2050 MHz) it is required to tune the

HMC1197LP7FE to the appropriate fundamental frequency, then select the appropriate output divider

setting (divide by 2/4/6.../60/62) in Reg 16h[5:0].

1.3.7.1 integer Mode

The HMC1197LP7FE is capable of operating in integer mode. For Integer mode set the following registers

a. Disable the Fractional Modulator, Reg 06h[11]=0

b. Bypass the Modulator circuit, Reg 06h[7]=1

In integer mode the VCO step size is fixed to that of the PD frequency. Integer mode typically has 3 dB

lower phase noise than fractional mode for a given PD operating frequency. Integer mode, however, often

requires a lower PD frequency to meet step size requirements. The fractional mode advantage is that

higher PD frequencies can be used, hence lower phase noise can often be realized in fractional mode.

Charge Pump offset should be disabled in integer mode Reg 09h[22:14] = 0h.

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