HMC1197LP7FE datasheet(40/57 Pages) AD

40 / 57 page

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Phone: 978-250-3343

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

2.9

reg 07h lock detect register deFault 200844 h

Bit

Type

Name

Width

Default

Description

[2:0]

R/W

lkd_wincnt_max

lock detect window

sets the number of consecutive counts of divided VCO that

must land inside the Lock Detect Window to declare LOCK

0: 5

1: 32

2: 96

3: 256

4: 512

5: 2048

6: 8192

7: 65535

[10:3]

R/W

Reserved

[11]

R/W

LD Enable

0: LD disable

1: LD enable

[19:12]

R/W

Reserved

[20]

R/W

Lock Detect Training

0 to 1 transition triggers the training. Lock Detect Training

is only required after changing Phase Detector frequency.

After changing PD frequency a toggle Reg 07h[20] from 0

to 1 retrains the Lock Detect.

[21]

R/W

CSP Enable

Cycle Slip Prevention enable.

When enabled, if the phase error becomes larger than

approx 70% of the PFD period, the charge-pump gain is

increased by approx 6mA for the duration of the cycle..

[23:22]

R/W

Reserved

2.10

reg 08h analog en register deFault 1bFFF h

Bit

Type

Name

Width

Default

Description

[4:0]

R/W

Reserved

31d

Reserved

[5]

R/W

GPO(General Purpose Output Pin

Enable)

0 - Pin LD_SDO disabled

1 - and RegFh[7]=1 , Pin LD_SDO is always driven, this is

required for use of GPO port

1 - and RegFh[7]=0 LDO_SPI is off if chip address

not equal to ‘000’b, allowing a shared SPI with other

compatible parts

[9:6]

R/W

Reserved

15d

Reserved

[10]

R/W

VCO Buffer and Prescaler

Bias Enable

0: VCO Buffer and Prescaler Bias Disable

1: VCO Buffer and Prescaler Bias Enable

Only applies to External VCO

[20:11]

R/W

Reserved

55d

Reserved

[21]

R/W

High Frequency Reference

Program to 1 for XTAL > 200 MHz, 0 otherwise

[22]

R/W

SDO Output Level

Output Logic Level on LD/SDO pin

0: 1.8 V Logic Levels

1: DVDD3V Logic Level

[23]

R/W

Reserved

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