HMC1197LP7FE datasheet(25/57 Pages) AD

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

table 11. reference Sensitivity table

Square Input

Sinusoidal Input

Reference Input

Frequency

(MHz)

Slew > 0.5V/ns

Recommended Swing (Vpp)

Recommended Power Range (dBm)

Recommended

Min

Max

Recommended

Min

Max

< 10

YES

0.6

2.5

YES

0.6

2.5

YES

0.6

2.5

YES

0.6

2.5

YES

100

YES

0.6

2.5

YES

150

0.9

2.5

YES

200

1.2

2.5

YES

Input referred phase noise of the PLL when operating at 50 MHz is between -148 and -150 dBc/Hz at 10

kHz offset depending upon the mode of operation. The input reference signal should be 10 dB better than

this floor to avoid degradation of the PLL noise contribution. It should be noted that such low levels are only

necessary if the PLL is the dominant noise contributor and these levels are required for the system goals.

1.3.3

reference Path ’r’ divider

The reference path “R” divider is based on a 14-bit counter and can divide input signals by values from 1

to 16,383 and is controlled via Reg 02h.

1.3.4

rF Path ’n’ divider

The main RF path divider is capable of average divide ratios between 219-5 (524,283) and 20 in fractional

mode, and 219-1 (524,287) to 16 in integer mode.

1.3.5

lock detect

The Lock Detect (LD) function indicates that the HMC1197LP7FE is indeed generating the desired

frequency. It is enabled by writing Reg 07h[11]=1. The HMC1197LP7FE provides LD indicator in one of two

ways:

•

As an output available on the LD_SDO pin of the HMC1197LP7FE, (Configuration is required to use

the LD_SDO pin for LD purpose, for more information please see “1.8 Serial Port Open Mode” and

“1.3.5.3 Configuring LD_SDO Pin for LD Output” section).

•

Or reading from Reg 12h[1], where Reg 12h[1] = 1 indicates locked and Reg 12h[1] = 0 indicates an

unlocked condition.

The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a

user specified time period (window), repeatedly. Either signal may arrive first, only the difference in arrival

times is significant. The arrival of the two edges within the designated window increments an internal

counter. Once the count reaches and exceeds a user specified value (Reg 07h[2:0]) the HMC1197LP7FE

declares lock.

Failure in registering the two edges in any one window resets the counter and immediately declares an

un-locked condition. Lock is deemed to be reestablished once the counter reaches the user specified

value (Reg 07h[2:0]) again.

1.3.5.1 lock detect configuration

Optimal spectral performance in fractional mode requires CP current and CP offset current configuration

discussed in detail in section “1.3.1”.

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