HMC1197LP7FE datasheet(39/57 Pages) AD

39 / 57 page

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

2.6

reg 04h Frequency register - Fractional Part deFault 0h

Bit

Type

Name

Width

Default

Description

[23:0]

R/W

Fractional Setting

Divider Fractional part (24 bit unsigned) see Fractional

Frequency

Tuning

Fractional Division Value = Reg4[23:0]/2^24

Used in Fractional Mode only

min 0

max 224-1 = FFFFFFh = 16,777,215d

2.7

reg 05h reserved

Bit

Type

Name

Width

Default

Description

[23:0]

R/W

Reserved

2.8

reg 06h delta Sigma Modulator register deFault 30F0ah

BIT

TYPE

NAME

Width

Default

DESCRIPTION

[1:0]

R/W

Reserved

Reserved, Program to 0h

[3:2]

R/W

DSM Order

Select the Delta Sigma Modulator Type

0: 1st order

1: 2nd Order

2: 3rd Order - Recommended

3: Reserved

[4]

R/W

Synchronous SPI Mode

0: Normal SPI Load - all register load on rising edge of SEN

1: Synchronous SPI - registers Reg 03h, Reg 04h , Reg 1Ah wait

to load synchronously on the next internal clock cycle.

Normally (When this bit is 0) SPI writes into the internal state

machines/counters happen asynchronously relative to the internal

clocks. This can create freq/phase disturbances if writing register

3, 4 or 1A. When this bit is enabled, the internal SPI registers are

loaded synchronously with the internal clock. This means that

the data in the SPI shifter should be held constant for at least 2

PFD clock periods after SEN is asserted to allow this retiming to

happen cleanly.

[5]

R/W

Exact Frequency Mode

Enable

1: Exact Frequency Mode Enabled

0: Exact Frequency Mode Disabled

[6]

R/W

Reserved

[7]

R/W

Fractional Bypass

0: Use Modulator, Required for Fractional Mode,

1: Bypass Modulator, Required for Integer Mode

Note: When enabled fractional modulator output is ignored, but

fractional modulator continues to be clocked if Reg 06h[11] =1.

This feature can be used to test the isolation of the digital frac-

tional modulator from the VCO output in integer mode.

[8]

R/W

Autoseed EN

1: loads the modulator seed (start phase) whenever the fractional

Reg 04h) is written

0: when fractional register (Reg 04h) write changes frequency,

modulator starts at previous value (phase)

[10:9]

R/W

Reserved

[11]

R/W

Delta Sigma Modulator

Enable

0: Disable DSM, used for Integer Mode

1: Enable DSM Core, required for Fractional Mode

[23:12]

R/W

Reserved

48d

30h

Reserved

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