HMC1197LP7FE datasheet(23/57 Pages) AD

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

1.3.1.3 charge Pump Phase offset

In Integer Mode, the phase detector operates with zero offset. The divided reference signal and the divided

VCO signal arrive at the phase detector inputs at the same time. Integer mode does not require any CP

Offset current. When operating in Integer Mode simply disable CP offset in both directions (Up and down),

by writing Reg 09h[22:21] = ‘00’b and set the CP Offset magnitude to zero by writingReg 09h[20:14]= 0.

In Fractional Mode CP linearity is of paramount importance. Any non-linearity degrades phase noise and

spurious performance.

In fractional mode, these non-linearities are eliminated by operating the PD with an average phase offset,

either positive or negative (either the reference or the VCO edge always arrives first at the PD ie. leads).

A programmable CP offset current source is used to add DC current to the loop filter and create the desired

phase offset. Positive current causes the VCO to lead, negative current causes the reference to lead.

The CP offset is controlled via Reg 09h[20:14]. The phase offset is scaled from 0 degrees, that is the

reference and the VCO path arrive in phase, to 360 degrees, where they arrive a full cycle late.

The specific level of charge pump offset current Reg 09h[20:14] is provided in (EQ 9). It is also plotted in

Figure 39 vs. PD frequency for typical CP Gain currents.

(

)

4.3 10

,0.25

Required CP Offset min

−







where:

FPD: Comparison frequency of the Phase Detector (Hz)

ICP: is the full scale current setting (A) of the switching charge pump (set in Reg 09h[6:0], [13:7]

(EQ 9)

100

200

300

400

500

600

700

100

PHASE DETECTOR FREQUENCY (MHz)

CP Current = 2.5 mA

CP Current = 2 mA

CP Current = 1 mA

Recommended

offset

current

frequency

for

typical

CP gain currents. Calculated using (EQ 9)

The required CP offset current should never exceed 25 % of the programmed CP current. It is recommended

to enable the Up Offset and disable the Down Offset by writing Reg 09h[22:21] = ‘10’b.

Operation with CP offset influences the required configuration of the Lock Detect function. Refer to the

description of Lock Detect function in section 1.3.5.

When operating with PD frequency >=80MHz, the CP Offset current should be disabled for the frequency

change and then re-enabled after the PLL has settled. If the CP Offset current is enabled during a

frequency change it may not lock.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

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