HMC1197LP7FE datasheet(35/57 Pages) AD

35 / 57 page

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

Figure 41. Serial Port Timing Diagram - WRITE

1.8.2

Serial Port read operation

A typical READ cycle is shown in Figure 42.

In general, the LD_SDO line is always active during the WRITE cycle. During any SPI cycle LD_SDO will

contain the data from the current address written in Reg 00h[4:0]. If Reg 00h[4:0] is not changed then the

same data will always be present on LD_SDO when an Open Mode cycle is in progress. If it is desired to

READ from a specific address, it is necessary in the first SPI cycle to write the desired address to Reg

00h[4:0], then in the next SPI cycle the desired data will be available on LD_SDO.

An example of the two cycle procedure to read from any address follows:

a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI

as shown in Figure 42. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on

the next cycle.

b. the slave (HMC1197LP7FE) shifts in data on SDI on the first 24 rising edges of SCK

c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5

falling edges of SCK (25-29). r4:r0=00000.

d. Slave shifts the register bits on the next 5 rising edges of SCK (25-29).

e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCK (30-32). Chip

address is always ‘000’b.

f. Slave shifts the chip address bits on the next 3 rising edges of SCK (30-32).

g. Master asserts SEN after the 32nd rising edge of SCK.

h. Slave registers the SDI data on the rising edge of SEN.

i. Master clears SEN to complete the the address transfer of the two part READ cycle.

j. If one does not wish to write data to the chip during the second cycle , then it is recommended to

simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle.

k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK.

l. Slave (HMC1197LP7FE) shifts the SDI data on the next 32 rising edges of SCK. On these same

edges, the slave places the desired read data (ie. data from the address specified in Reg 00h[4:0] of

the first cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling the

LD output.

m. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock

Detect on LD_SDO.

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