HMC1197LP7FE datasheet(32/57 Pages) AD

32 / 57 page

For price, delivery, and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

If (EQ 16) is satisfied for at least two of the equally spaced interval (channel) frequencies fVCO1,fVCO2,fVCO3,...

fVCON, as it is above, Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies,

and can be configured as follows:

Reg 03h =

2800.2 10

61.44 10

VCO

floor







Reg 0Ch =

(

)

(

)

(

)

61.44 10

3072

20000

gcd 100 10 ,61.44 10

gcd

VCOk

dC h

××

−

where (fVCOk+1 - fVCOk) is the desired channel spacing (100 kHz in this example).

To program Reg 04h the closest integer-N boundary frequency fN that is less than the smallest

channel VCO frequency fVCO1 must be calculated. fN = floor(fVCO1/fPD). Using the current example:

2800.2 10

45 61.44 10

2764.8

61.44 10

floor

MHz







×=

Then

Reg 04h

(

)

(

)

for channel 1 where

2800.2

2800.2 10

2764.8 10

9666560

938000

61.44 10

VCO

ceil

MHz

ceil













































−

×−

To change from channel 1 (fVCO1 = 2800.2 MHz) to channel 2 (fVCO2 = 2800.3 MHz), only

Reg 04h needs to be programmed, as long as all of the desired exact frequencies fVCOk (Figure 40)

fall between the same integer-N boundaries (fN < fVCOk < fN+1). In that case

Reg 04h =

(

)

2800.3 10

2764.8 10

9693867

61.44 10

ceil

EAABh

























×−

, and so on.

1.3.8

Seed register

The start phase of the fractional modulator digital phase accumulator (DPA) may be set to any desired

phase relative to the reference frequency, The phase is programmed in Reg 1Ah, and Exact Frequency

Mode is required. Phase = 2π x Reg1Ah/(224) via the seed register Reg 1Ah[23:0]. The HMC1197LP7FE

will automatically reload the start phase (seed value) into the DPA every time a new fractional frequency is

selected. Certain zero or binary seed values may cause spurious energy correlation at specific frequencies.

For most cases a random, or non zero, non-binary start seed is recommended.

1.4

Soft reset & Power-on reset

The HMC1197LP7FE features a hardware Power on Reset (POR). All chip registers will be reset to default

states approximately 250 µs after power up.

The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg 00h.

1.5

Power down Mode

Power down the HMC1197LP7FE by pulling CEN pin (pin 17) low (assuming no SPI overrides(Reg

01h[0]=1)). This will result in all analog functions and internal clocks disabled. Current consumption will

typically drop below 10 µA in Power Down state. The serial port will still respond to normal communication

in Power Down mode.

It is possible to ignore the CEN pin, by setting Reg 01h[0]=0. Control of Power Down Mode then comes

from the serial port register Reg 01h[1].

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D

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