HMC1197LP7FE datasheet(16/57 Pages) AD

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

1.0

theory of operation

The block diagram of HMC1197LP7FE PLL with Integrated VCO is shown in Figure 35

Figure 35. HMC1197LP7FE PLL VCO Block Diagram

1.1

Pll overview

The PLL divides down the VCO output to the desired comparison frequency via the N-divider (integer value

set in Reg 03h, fractional value set in Reg 04h), compares the divided VCO signal to the divided reference

signal (reference divider set in Reg 02h) in the Phase Detector (PD), and drives the VCO tuning voltage

via the Charge Pump (CP) (configured in Reg 09h) to the VCO subsystem. Some of the additional PLL

subsystem functions include:

•

Delta Sigma configuration (Reg 06h)

•

Exact Frequency Mode (Configured in Reg 0Ch, Reg 06h,Reg 03h, and Reg 04h)

•

Lock Detect (LD) Configuration (Reg 07h to configure LD, and Reg 0Fh to configure LD_SDO output

pin)

•

External CEN pin used as hardware enable pin.

Typically, only writes to the divider registers (integer part Reg 03h, fractional part Reg 04h,VCO Divide

Ratio part Reg 04h) are required for HMC1197LP7FE output frequency changes.

Divider registers of the PLL (Reg 03h, and Reg 04h), set the fundamental frequency (2050 MHz to 4100

MHz) of the VCO. Output frequencies ranging from 33 MHz to 2050 MHz are generated by tuning to the

appropriate fundamental VCO frequency (2050 MHz to 4100 MHz) by programming N divider (Reg 03h,

and Reg 04h), and programming the output divider (divide by 1/2/4/6.../60/62, programmed in Reg 16h) in

the VCO register.

For detailed frequency tuning information and example, please see “1.3.7 Frequency Tuning” section.

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