HMC1197LP7FE datasheet(13/57 Pages) AD

13 / 57 page

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HMC1197LP7FE

v03.0314

Wideband direct Quadrature Modulator

w/ Fractional-n Pll & Vco, 100 - 4000 MHz

table 8. Pin descriptions

Pin Number

Function

Description

VDDCP

Power Supply for charge pump analog section, 5.0V nominal.

BIAS

External bypass decoupling for precision bias circuits, 5.0V nominal.

3,4

CP1,CP2

Charge Pump Outputs.

RVDD

Reference Supply, 3.3V nominal.

XREFP

Reference Input. DC bias is generated internally. Normally AC coupled externally.

DVDD

DC Power Supply for Digital (CMOS) Circuitry, 3.3V nominal.

8, 13, 14, 22,

23, 24, 28,

29, 30, 41, 42

N/C

The pins are not connected internally; however, all data shown herein was measured with these pins

connected to RF/DC ground externally.

EN_MOD

This pin has a 10 Kohm pulldown resistor to GND. When connected to GND or left floating the chip is

fully enabled. When connected to VCC the LO amplifiers and the mixers

are disabled.

IF1P

Supply voltage for the LO and mixer stage, 5.0V nominal.

11, 12

QN, QP

Q channel differential baseband input.These are high impedance ports. The nominal recommended

bias voltage is 0.45V (0.4V-0.5V)[1].The nominal recommended baseband input AC voltage is 1.3V

peak-to-peak differential.By adjusting the DC offsets on ports QN & QP , the Carrier Suppression of the

device can be optimized for a specific frequency band and LO power level. The typical offset voltege for

optimization is less than 15 mV.

The amplitude and phase difference between The I and Q inputs can be adjusted in order to optimize the

Sideband Suppression for a specific frequency band and LO power level

15, 16, 17,

18, 20

GND

These pins and package base must be connected to RF and DC ground.

RFOUT

DC coupled and matched to 50 Ohms.

Output requires an external DC blocking capacitor.

VCC3

Supply voltage for the output stages, 5.0V nominal.

25, 26

IP, IN

I channel differential baseband input. These are high impedance ports. The nominal recommended bias

voltage is 0.45V (0.4V-0.5V). The nominal recommended baseband input AC voltage is 1.3V peak-to-

peak differential.By adjusting the DC offsets on ports IN & IP , the Carrier Suppression of the device can

be optimized for a specific frequency band and LO power level. The typical offset voltege for optimization

is less than 15 mV.

The amplitude and phase difference between The I and Q inputs can be adjusted in order to optimize the

Sideband Suppression for a specific frequency band and LO power level

Supply pin for low pass filter, 3.3V nominal.

CHIP_EN

Chip Enable. Connect to logic high for normal operation.

32, 33

LON, LOP

LO outputs. AC coupled and matched to 50 Ohms single ended. Do not need external DC decoupling

capacitors. The ports could be single-ended or differential.

VCC1

VCO analog supply 1, 5.0V nominal.

VCC2

VCO analog supply 2, 5.0V nominal.

VTUNE

VCO Varactor. Tuning Port Input.

SEN

PLL Serial Port Enable (CMOS) Logic Input.

SDI

PLL Serial Port Data (CMOS) Logic Input.

SCK

PLL Serial Port Clock (CMOS) Logic Input.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

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