ADP5053ACPZ-R7 datasheet(28/37 Pages) AD

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Data Sheet

ADP5053

Rev. B | Page 27 of 36

SwitchingLoss (PSW)

Switching losses are associated with the current drawn by the

driver to turn the power devices on and off at the switching

frequency. Each time a power device gate is turned on or off,

the driver transfers a charge from the input supply to the gate,

and then from the gate to ground. Use the following equation to

estimate the switching loss:

PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW

where:

CGATE_HS is the gate capacitance of the high-side MOSFET.

CGATE_LS is the gate capacitance of the low-side MOSFET.

fSW is the switching frequency.

TransitionLoss (PTRAN)

Transition losses occur because the high-side MOSFET cannot

turn on or off instantaneously. During a switch node transition,

the MOSFET provides all the inductor current. The source-to-

drain voltage of the MOSFET is half the input voltage, resulting

in power loss. Transition losses increase with both load and input

voltage and occur twice for each switchingcycle.Use the following

equation to estimate the transition loss:

PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW

where:

tR is the rise time of the switch node.

tF is the fall time of the switch node.

Thermal Shutdown

Channel 1 and Channel 2 store the value of the inductor current

only during the on time of the internal high-side MOSFET.

Therefore, a small amount of power (as well as a small amount

of input rms current) dissipates inside the ADP5053, which

reduces thermal constraints.

However, when Channel 1 and Channel 2 are operating under

maximum load with high ambient temperature and high duty

cycle, the input rms current can become very large and cause

the junction temperature to exceed the maximum junction

temperature of 125°C. If the junction temperature exceeds

150°C, the regulator enters thermal shutdown and recovers

when the junction temperature falls below 135°C.

JUNCTION TEMPERATURE

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to power dissipation, as shown in the following

equation:

TJ = TA + TR

where:

TJ is the junction temperature.

TA is the ambient temperature.

TR is the rise in temperature of the package due to power

dissipation.

The rise in temperature of the package is directly proportional

to the power dissipation in the package. The proportionality

constant for this relationship is the thermal resistance from the

junction of the die to the ambient temperature, as shown in the

following equation:

TR = θJA × PD

where:

TR is the rise in temperature of the package.

θJA is the thermal resistance from the junction of the die to the

ambient temperature of the package (see Table 6).

PD is the power dissipation in the package.

An important factor to consider is that the thermal resistance

value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of

copper, as specified in the JEDEC standard, whereas real-world

applications may use PCBs with different dimensions and a

different number of layers.

It is important to maximize the amountof copper used to remove

heat from the device. Copper exposed to air dissipates heat better

than copper used in the inner layers. Connect the exposed pad

to the ground plane with several vias.

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