ADP5053

Data Sheet

Rev. B | Page 36 of 36

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4.

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

1

0.50

BSC

BOTTOM VIEW

TOP VIEW

PIN 1

INDICATOR

48

13

24

36

37

PIN 1

INDICATOR

5.70

5.60 SQ

5.50

0.50

0.40

0.30

SEATING

PLANE

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.203 REF

COPLANARITY

0.08

0.30

0.25

0.18

7.10

7.00 SQ

6.90

0.20 MIN

5.50 REF

END VIEW

EXPOSED

PAD

Figure 55. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

7 mm × 7 mm Body, Very Very Thin Quad

(CP-48-13)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature Range

Package Description

ADP5053ACPZ-R7

−40°C to +125°C

48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

CP-48-13

ADP5053-EVALZ

Evaluation Board

2 Table 16 lists the factory default options for the device. To order a device with options not listed, contact your local Analog Devices sales or distribution representative.

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D11636-0-10/16(B)