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ADP5053ACPZ-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADP5053ACPZ-R7
功能描述  Integrated Power Solution with Quad Buck
PDF  37 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5053ACPZ-R7 数据表(HTML) 18 Page - Analog Devices

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Data Sheet
ADP5053
Rev. B | Page 17 of 36
SEPARATE SUPPLYAPPLICATIONS
The ADP5053 supports separate input voltages for the four
buck regulators. This means that the input voltages for the four
buck regulators can be connected to different supply voltages.
The PVIN1 voltage provides the power supply for the internal
regulators and the control circuitry. Therefore, if the user plans
to use separate supply voltages for the buck regulators, the PVIN1
voltage must be above the UVLO threshold before the other
channels begin to operate.
To ensure that PVIN1 is high enough to support the outputs in
regulation, use precision enabling to monitor the PVIN1 voltage
and to delay the startup of the outputs. For more information,
see the Precision Enabling section.
The ADP5053 supports cascading supply operation for the four
buck regulators. As shown in Figure 32, PVIN2, PVIN3, and
PVIN4 are powered from the Channel 1 output (VOUT1). In this
configuration, the Channel 1 output voltage must be higher
than the UVLO threshold for PVIN2, PVIN3, and PVIN4.
PVIN1
BUCK 1
BUCK 2
VOUT1
PVIN2
TO
PVIN4
VOUT2 TO VOUT4
VIN
Figure 32. Cascading Supply Application
LOW-SIDEDEVICESELECTION
The buck regulators in Channel 1 and Channel 2 integrate 4 A
high-side power MOSFET and low-side MOSFET drivers. The
N-channel MOSFETs selected for use with the ADP5053 must be
compatible with the synchronized buck regulators. In general, a
low RDSON N-channel MOSFET achieves higher efficiency;dual
MOSFETs in onepackage (for both Channel 1 and Channel 2) are
recommended to save space on the printed circuit board (PCB).
For more information, see the Low-Side Power Device Selection
section.
BOOTSTRAP CIRCUITRY
Each buck regulator in the ADP5053 has an integrated bootstrap
regulator. The bootstrap regulator requires a 0.1 µF ceramic
capacitor (X5R or X7R) between the BSTx and SWx pins to
provide the gate drive voltage for the high-side MOSFET.
ACTIVE OUTPUT DISCHARGESWITCH
Each buck regulator in the ADP5053 integrates a discharge switch
from the switching node to ground. This switch is turned on
when its associated regulator is disabled, which helps todischarge
the output capacitor quickly. The typical value of the discharge
switch is 250 Ω for Channel 1 to Channel 4.
Enable or disable the discharge switch function for all four buck
regulators by factory fuse.
PRECISION ENABLING
The ADP5053 has an enable control pin for each regulator. The
enable control pin(ENx) features a precision enable circuit with a
0.8 V reference voltage.A voltage greater than 0.8 V at the ENxpin
enables the regulator. A voltage less than 0.725 V at the ENx pin
disables the regulator. An internal 1MΩ pull-down resistor
prevents errors when the ENx pin is left floating.
The precision enable threshold voltage allows easy sequencing
of channels within the device, as well as sequencing between the
ADP5053 and other input/outputsupplies. The ENx pin can also
be used as a programmable UVLO input using a resistor divider
(see Figure 33). For more information, see the Programming
the UVLO Input section.
0.8V
DEGLITCH
TIMER
INTERNAL
ENABLE
ENx
R1
R2
1MΩ
INPUT/OUTPUT
VOLTAGE
ADP5053
Figure 33. Precision Enable Diagram for One Channel
OSCILLATOR
The switching frequency (fSW) of the ADP5053 can be set to a
value from 250 kHz to 1.4 MHz by connecting a resistor from
the RT pin to ground. Calculate the value of the RT resistor as
follows:
RRT (kΩ) = [14,822/fSW (kHz)]1.081
Figure 34 shows the typical relationship between the switching
frequency (fSW) and the RT resistor. The adjustable frequency
allows users to make decisions based on the trade-off between
efficiency and solution size.
1.6M
1.4M
1.2M
1.0M
800k
600k
400k
200k
0
0
20
40
RT RESIST
OR (kΩ)
60
80
Figure 34. Switching Frequency vs. RT Resistor
For Channel 1 and Channel 3, the frequencycan be set to half the
master switching frequency set by the RT pin. This setting can be
selected by factory fuse. If the master switching frequency is less
than 250 kHz, this halving of the frequency for Channel 1 or
Channel 3 is not recommended.



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