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ADP5053

Data Sheet

Rev. B | Page 22 of 36

Watchdog Input

The ADP5053 features a watchdog timer that monitors

microprocessor activity. A timer circuit is cleared with every

low to high or high to low logic transition on the watchdog

input pin (WDI), which detects pulses as short as 80 ns. If the

timer proceeds through the preset watchdog timeout period (tWD),

reset is asserted. The microprocessor is required to toggle the WDI

pin to avoid being reset. Therefore, failure of the microprocessor

to toggle the WDI pin within the timeout period indicates a

code execution error, and the reset pulse generated restarts the

micro-processor in a known state. Four options are available for the

watchdog timeout period via the factory fuse: 6.3 ms, 102 ms,

1600 ms (default), or 25.6 sec.

In addition to the logic transition on the WDI pin, the watchdog

timer is also cleared by a reset assertion due to an undervoltage

condition on VOUT2. When a reset is asserted, the watchdog timer

clears, and the timer does not begin counting again until the

reset is deasserted. Disable the watchdog timer by leaving WDI

floating or by three-stating the WDI driver. Figure 44 shows the

watchdog timing diagram.

VTH

VOUT2

WDI

VOUT2

tRP

tWD

RSTO

Figure 44. Watchdog Timing Diagram

Manual Reset Input

The ADP5053 features a manual reset input (MR pin, active low)

with two operation modes: processor manual reset mode or

power on/off switch mode. The default setting is the processor

manual reset mode; however, MR operation mode selection can

be configured by factory fuse.

The MR input has an internal 55 kΩ pull-up resistor so that the

input remains high when unconnected. To generate a reset,

connect an external push-button switch between MR and

ground. Noise immunity is provided on the MR input, and fast,

negative going transients of up to 100 ns (typical) are ignored. A

0.1 μF capacitor between MR and ground provides additional

noise immunity.

Processor Manual Reset Mode

In processor manual reset mode, when MR is driven low, the

reset output is asserted. When MR transitions from low to high,

the reset remains asserted for the duration of the reset active

timeout period (tRP) before deasserting. Figure 45 shows the

behavior of the MR pin in processor manual reset mode.

MR EXTERNALLY

DRIVEN LOW

RSTO

VCC

tRP

VTH

Figure 45. MR Timing Diagram in Processor Reset Mode

Power On/Off Switch Mode

In power on/off switch mode, when MR is driven low for more

than 4 sec, all channels in the ADP5053 shut down, and the

internal control registers reset. In this shutdown standby condition,

if MR is driven low for 500 ms again, all channels in the

ADP5053 restart according to the individual ENx pin status.

Figure 46 shows the MR timing diagram in power on/off switch

mode.

To prepare for automatic startup, clear the MR shutdown

condition by pulling down all external ENx pins.

500ms

BLANKING

tRP

SEQUENCE

START-UP

SEQUENCE

START-UP

MR SHUTDOWN BY 4s

MR TIMER

MR SHUTDOWN

MODE

FORCE RSTO

LOW IN SHUTDOWN

MODE

RESTART ALL POWER

BY 500ms MR TIMER

(USED AS ON/OFF SWITCH)

VOUT1 TO

VOUT4

PVINx/ENx

RSTO

Figure 46. MR Timing Diagram in Power On/Off Switch Mode

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