ADP5053ACPZ-R7 datasheet(19/37 Pages) AD

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ADP5053

Data Sheet

Rev. B | Page 18 of 36

Phase Shift

The phase shift between Channel 1 and Channel 2 and between

Channel 3 and Channel 4 is 180°.Therefore,Channel3 is in phase

with Channel 1, and Channel 4 is in phase with Channel 2 (see

Figure 35). This phase shift maximizes the benefits of out-of-phase

operation by reducing the input ripple current and lowering the

ground noise.

CHANNEL 2

CHANNEL 1

(½

fSW

OPTIONAL)

CHANNEL 4

180° PHASE SHIFT

0° REFERENCE

0° PHASE SHIFT

180° PHASE SHIFT

CHANNEL 3

(½

fSW

OPTIONAL)

Figure 35. Phase Shift Diagram, Four Buck Regulators

SYNCHRONIZATION INPUT/OUTPUT

The switching frequencyof the ADP5053can be synchronized

to an external clock with a frequency range from 250 kHz to

1.4 MHz. The ADP5053 automatically detects the presence

of an external clock applied to the SYNC/MODE pin, and the

switching frequency transitions smoothly to the frequency of

the external clock. When the external clock signal stops, the

device automatically switches back to the internal clock and

continues to operate.

Note that the internal switching frequency set bythe RT pin must

be programmed to a value that is close to the external clock value

for effective synchronization; the suggested frequencydifference

is less than ±15% in typical applications.

The SYNC/MODE pin can be configured as a synchronization

clock output by factory fuse. Regardless of the synchronization

configuration method, the SYNC/MODE pin generates a

positive clock pulse with a 50% duty cycle and a frequencyequal

to the internal switching frequency set by the RT pin. There is a

short delay time (approximately 15% of tSW) from the generated

synchronization clock to the Channel 1 switching node.

Figure 36 shows two ADP5053 devices configured for frequency

synchronization mode: one ADP5053 device is configured as

the clock output to synchronize another ADP5053 device. It is

recommended that a 100 kΩ pull-up resistor be used to prevent

logic errors when the SYNC/MODE pin remains floating.

ADP5053

100kΩ

VREG

SYNC/MODE

ADP5053

Figure 36. Two ADP5053 Devices Configured for Synchronization Mode

In the configuration shown in Figure 36, the phase shift between

Channel 1 of the first ADP5053 device and Channel 1 ofthe

second ADP5053 device is 0° (see Figure 37).

CH3 5.00V BW

CH1 2.00V BW

CH2 5.00V BW

M400ns

A CH1

560mV

SW1

AT FIRST

ADP5053

SW1

AT SECOND

ADP5053

SYNC-OUT

AT FIRST

ADP5053

Figure 37. Waveforms of Two ADP5053 Devices Operating

in Synchronization Mode

SOFT START

The buck regulators in the ADP5053 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

is typically fixed at 2 ms for each buck regulator when the SS12

and SS34 pins are tied to VREG.

To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect

a resistor divider from the SS12 or SS34 pin to the VREG pin and

ground (see Figure 38). This configurationmay be required to

accommodate a specific start-up sequence or an application with

a large output capacitor.

LEVEL DETECTOR

AND DECODER

VREG

TOP

RESISTOR

BOTTOM

RESISTOR

SS12

SS34

ADP5053

Figure 38. Level Detector Circuit for Soft Start

Use the SS12 pin to program the soft start time and parallel

operation for Channel 1 and Channel 2. Use the SS34 pin to

program the soft start time for Channel 3 and Channel 4.

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