ADP5053ACPZ-R7 datasheet(27/37 Pages) AD

27 / 37 page

ADP5053

Data Sheet

Rev. B | Page 26 of 36

COMPENSATION COMPONENTSDESIGN

For the peak current mode control architecture, simplify the

power stage as a voltage controlled current source that supplies

current to the output capacitor and load resistor. The simplified

loop is composed of one domain pole and a zero contributed by

the output capacitor ESR. The control-to-output transfer

function is shown in the following equations:

























COMP

OUT

)

(

)

(

)

(

OUT

ESR

(

)

OUT

ESR

where:

AVI = 10 A/V for Channel 1 or Channel 2, and 3.33 A/V for

Channel 3 or Channel 4.

R is the load resistance.

s = the frequency domain factor.

RESR is the equivalent series resistance of the output capacitor.

COUT is the output capacitance.

The ADP5053 uses a transconductance amplifier as the error

amplifier to compensate the system. Figure 47 shows the

simplified peak current mode control small signal circuit.

RESR

–

CCP

COUT

RTOP

RBOT

–

AVI

VOUT

VCOMP

VOUT

Figure 47. Simplified Peak Current Mode Control Small Signal Circuit

The compensation components, RC and CC, contribute a zero;

RC and the optional CCP contribute an optional pole.

The closed-loop transfer equation is as follows:

)

(

)

(

TOP

BOT













−

The following guidelines define how the compensation

components (RC, CC, and CCP) selection for ceramic output

capacitor applications.

1. Determine the cross frequency (fC). Generally, fC is between

fSW/12 and fSW/6.

2. Calculate RC using the following equation:

OUT

3. Place the compensation zero at the domain pole (fP).

Calculate CC using the following equation:

(

)

OUT

ESR

4. CCP is optional. It can be used to cancel the zero caused by

the ESR of the output capacitor. Calculate CCP using the

following equation:

OUT

ESR

POWER DISSIPATION

The total power dissipation in the ADP5053 simplifies to

PD = PBUCK1 + PBUCK2 + PBUCK3 + PBUCK4

Buck RegulatorPower Dissipation

The power dissipation (PLOSS) for each buck regulator includes

power switch conduction losses (PCOND), switching losses (PSW),

and transition losses (PTRAN). Other sources of power dissipation

exist, but these sources are generally less significant at the high

output currents of the application thermal limit.

Use the following equation to estimate the power dissipation of

the buck regulator:

PLOSS = PCOND + PSW + PTRAN

Power Switch ConductionLoss (PCOND)

Power switch conduction losses are caused by the flow of output

current through both the high-side and low-side power switches,

each of which has its own internal on resistance (RDSON).

Use the following equation to estimate the power switch

conduction loss:

PCOND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2

where:

RDSON_HS is the on resistance of the high-side MOSFET.

RDSON_LS is the on resistance of the low-side MOSFET.

D is the duty cycle (D = VOUT/VIN).

ADP5053ACPZ-R7 数据表(PDF) 27 Page - Analog Devices

ADP5053ACPZ-R7 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载