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ADP5053

Data Sheet

Rev. B | Page 16 of 36

THEORY OF OPERATION

The ADP5053 is a micropower management unit that combines

four high performance buck regulators in a 48-lead LFCSPpackage

to meet demanding performance and board space requirements.

The device enables direct connection to high input voltages up

to 15.0 V with no preregulators to make applications simpler

and more efficient.

BUCK REGULATOR OPERATIONAL MODES

Pulse-Width Modulation (PWM) Mode

In PWM mode, the buck regulators in the ADP5053operateat a

fixed frequency; this frequency is set by an internal oscillatorthat

is programmed by the RT pin.At thestart ofeach oscillator cycle,

the high-side MOSFET turns on and sends a positive voltage

across the inductor. The inductor current increases until the

current sense signal exceeds the peak inductor current threshold

that turns off the high-side MOSFET; this threshold is set by the

error amplifier output.

During the high-side MOSFET off time, the inductor current

decreases through the low-side MOSFET until the next oscillator

clock pulse starts a new cycle.The buck regulators in the ADP5053

regulate the output voltage byadjustingthe peak inductor current

threshold.

Power Save Mode (PSM)

To achieve higher efficiency, the buck regulators in the ADP5053

smoothly transition to variable frequencyPSMoperation when

the output load falls below the PSM current threshold. When

the output voltage falls below regulation, the buck regulator

enters PWM mode for a few oscillator cycles until the voltage

increases to within regulation. During the idle time between

bursts, the MOSFET turns off, and the output capacitor supplies

all the output current.

The PSM comparator monitors the internal compensationnode,

which represents the peak inductor current information. The

average PSM current threshold depends on the input voltage

(VIN), the output voltage (VOUT), the inductor, and the output

capacitor. Because the output voltage occasionally falls below

regulation and then recovers, the output voltage ripple in PSM

operation is larger than the ripple in the forced PWM mode of

operation under light load conditions.

Forced PWM and Automatic PWM/PSMModes

The buck regulators can be configured to always operate in PWM

mode using the SYNC/MODE pin. In forced PWM (FPWM)

mode, the regulator continues to operate at a fixed frequency

even when the output current is below the PWM/PSMthreshold.

In PWM mode, efficiencyis lower when compared to PSM mode

under light load conditions. The low-side MOSFET remains on

when the inductor current falls to less than 0 A, causing the

ADP5053 to enter continuous conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM/PSM mode using the SYNC/MODE pin. In automatic

PWM/PSM mode, the buck regulators operate in either PWM

mode or PSM mode, depending on the outputcurrent. When the

average output current falls below the PWM/PSM threshold,

the buck regulator enters PSM mode operation; in PSM mode,

the regulator operates with a reduced switching frequency to

maintain high efficiency. The low-side MOSFET turns off when

the output current reaches 0 A, causing the regulator to operate

in discontinuous mode (DCM).

When the SYNC/MODE pin is connected to VREG, the device

operates in forced PWM (FPWM) mode. When the SYNC/

MODE pin is connected to ground, the device operates in

automatic PWM/PSM mode.

ADJUSTABLEAND FIXED OUTPUT VOLTAGES

The ADP5053 provides adjustable and fixed output voltage

settings via factory fuse. For the adjustable output settings, use

an external resistor divider to set the desired output voltage via

the feedback referencevoltage (0.8V for Channel1 to Channel 4).

For the fixed output settings, the feedback resistor divider is

built into the ADP5053,and the feedback pin (FBx) must be tied

directly to the output. Table 8 lists the available fixed output

voltage ranges for each buck regulator channel.

Table 8. Fixed Output Voltage Ranges

Channel

Fixed Output Voltage Range

Channel 1

0.85 V to 1.6 V in 25 mV steps

Channel 2

3.3 V to 5.0 V in 300 mV or 200 mV steps

Channel 3

1.2 V to 1.8 V in 100 mV steps

Channel 4

2.5 V to 5.5 V in 100 mV steps

The output range can also be programmed by factory fuse. If a

different output voltage range is required, contact your local

Analog Devices, Inc., sales or distribution representative.

INTERNAL REGULATORS (VREG AND VDD)

The internal VREG regulator in the ADP5053 provides a stable

5.1 V power supply for the bias voltage of the MOSFET drivers.

The internal VDD regulator in the ADP5053 provides a stable

3.3 V power supply for internal control circuits. Connecta 1.0 µF

ceramic capacitor between VREG and ground; connect another

1.0 µF ceramic capacitor between VDD and ground. The internal

VREG and VDD regulators are active as long as PVIN1 is available.

The internal VREG regulator can provide a total load of 95 mA

including the MOSFET driving current, and it can be used as

an always alive 5.1 V power supply for a small system current

demand. The current-limit circuit is included in the VREG

regulator to protect thecircuit whenthe device is heavilyloaded.

The VDD regulator is strictly for internal circuit use and is not

recommended for other purposes.

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