Integrated Power Solution with Quad Buck

Regulators and Supervisory Circuits

Data Sheet

ADP5053

Rev. B

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FEATURES

Wide input voltage range: 4.5 V to 15.0 V

±1.5% output accuracy over full temperature range

250 kHz to 1.4 MHz adjustable switching frequency

Adjustable/fixed output options via factory fuse

Power regulation

Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A

sync buck regulators with low-side FET driver

Channel 3 and Channel 4: 1.2 A sync buck regulators

Single 8 A output (Channel 1 and Channel 2 operated in parallel)

Precision enable with 0.8 V accurate threshold

Active output discharge switch

FPWM or automatic PWM/PSM selection

Frequency synchronization input or output

Optional latch-off protection on OVP/OCP failure

Power-good flag on selected channels

UVLO, OCP, and TSD protection

Open-drain processor reset with external adjustable

threshold monitoring

Watchdog refresh input

Manual reset input

APPLICATIONS

Small cell base stations

FPGA and processor applications

Security and surveillance

Medical applications

TYPICAL APPLICATION CIRCUIT

CHANNEL 2

BUCK REGULATOR

(1.2A/2.5A/4A)

CHANNEL 3

BUCK REGULATOR

(1.2A)

OSCILLATOR

INT VREG

100mA

Q1

Q2

L1

L2

VREG

SYNC/MODE

RT

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

L3

BST3

SW3

FB3

PGND3

L4

VREG

BST4

SW4

FB4

PGND4

VREG

PVIN1

COMP1

EN1

PVIN2

COMP2

EN2

PVIN3

SS34

COMP3

EN3

PVIN4

COMP4

EN4

C2

C1

C4

C3

C5

C6

C7

C8

C9

C10

C11

C12

C13

4.5V TO 15V

VOUT1

VOUT2

VOUT3

VOUT4

VOUTx

VREG

EXPOSED PAD

SS12

C0

VDD

WATCHDOG

AND RESET

VTH

WDI

MR

RSTO

ADP5053

CHANNEL 1

BUCK REGULATOR

(1.2A/2.5A/4A)

CHANNEL 4

BUCK REGULATOR

(1.2A)

PWRGD

Figure 1.

GENERAL DESCRIPTION

The ADP5053 combines four high performance buck regulators,a

supervisory circuit, a watchdog timer, and a manual reset in a

48-lead LFCSP package thatmeets demandingperformance and

board space requirements. The device enables direct connection

to high input voltages up to 15.0 V with no preregulators.

Channel 1 and Channel 2 integrate high-sidepower MOSFET and

low-side MOSFET drivers.External NFETs can be used in low-side

power devices to achieve an efficiency optimized solution and

deliver a programmable outputcurrentof 1.2A, 2.5A, or 4 A.

Combining Channel 1 and Channel 2 in a parallel configuration

can provide a single outputwith up to 8 A ofcurrent.

Channel 3 and Channel 4 integrate both high-side and low-side

MOSFETs to deliver an output current of 1.2 A.

The switching frequency of the ADP5053 can be programmed

or synchronized to an external clock. The ADP5053 contains a

precision enable pinon each channel for easy power-up sequencing

or adjustable UVLO threshold.

The ADP5053 contains supervisory circuits that monitor the

voltage level. The watchdog timer can generate a reset if the

WDI pin is not toggled withina preset timeout period.Processor

reset mode or system power on/off switch mode can be selected

for manual reset functionality.

Table 1. Family Models

Model

Channels

Package

ADP5050

Four bucks, one LDO

Yes

48-Lead LFCSP

ADP5051

Four bucks, supervisory

Yes

48-Lead LFCSP

ADP5052

Four bucks, one LDO

No

48-Lead LFCSP

ADP5053

Four bucks, supervisory

No

48-Lead LFCSP

ADP5054

Four high current bucks

No

48-Lead LFCSP