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ADP5053ACPZ-R7 数据表(PDF) 13 Page - Analog Devices

部件名 ADP5053ACPZ-R7
功能描述  Integrated Power Solution with Quad Buck
PDF  37 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5053ACPZ-R7 数据表(HTML) 13 Page - Analog Devices

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ADP5053
Data Sheet
Rev. B | Page 12 of 36
0
10
20
30
40
50
60
70
80
90
100
0
0.2
0.4
0.6
0.8
1.0
1.2
IOUT (A)
fSW = 1.0MHz
fSW = 600kHz
fSW = 300kHz
Figure 10. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V,
FPWM Mode
0
10
20
30
40
50
60
70
80
90
100
0.01
0.1
1
2
IOUT (A)
VOUT = 1.2V, FPWM
VOUT = 1.2V, AUTO PWM/PSM
VOUT = 1.8V, FPWM
VOUT = 1.8V, AUTO PWM/PSM
VOUT = 3.3V, FPWM
VOUT = 3.3V, AUTO PWM/PSM
Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,
FPWM and Automatic PWM/PSM Modes
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0
1
2
3
4
IOUT (A)
Figure 12. Channel 1 Load Regulation, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz,
FPWM Mode
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
INPUT VOLTAGE (V)
Figure 13. Channel 1 Line Regulation, VOUT = 3.3 V, IOUT = 4 A,
fSW = 600 kHz, FPWM Mode
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0
0.2
0.4
0.6
0.8
1.0
1.2
IOUT (A)
Figure 14. Channel 3 Load Regulation, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz,
FPWM Mode
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
INPUT VOLTAGE (V)
Figure 15. Channel 3 Line Regulation, VOUT = 3.3 V, IOUT = 1 A,
fSW = 600 kHz, FPWM Mode



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