ADP5053ACPZ-R7 datasheet(20/37 Pages) AD

20 / 37 page

Data Sheet

ADP5053

Rev. B | Page 19 of 36

Table 9 provides the required resister values to set the soft start

time.

Table 9. Soft Start Time Set by the SS12 and SS34 Pins

Soft Start Time

RTOP (kΩ) RBOT (kΩ) Channel 1 Channel 2 Channel 3 Channel 4

N/A1

2 ms

100

600

2 ms

Parallel

2 ms

4 ms

200

500

2 ms

8 ms

2 ms

8 ms

300

400

4 ms

2 ms

4 ms

2 ms

400

300

4 ms

500

200

8 ms

2 ms

4 ms

8 ms

600

100

8 ms

Parallel

8 ms

2 ms

N/A1

8 ms

1 N/A = not applicable.

PARALLEL OPERATION

The ADP5053 supports two-phase parallel operation ofChannel 1

and Channel 2 to providea singleoutput with up to 8 A of current.

Take the followingactions to configure Channel 1and Channel 2 as

a two-phase single output in parallel operation (see Figure 39):

•

Use the SS12 pin to select parallel operation as specified in

Table 9.

•

Leave the COMP2 pin open.

•

Use the FB1 pin to set the output voltage.

•

Connect the FB2 pin to ground (FB2 is ignored).

•

Connect the EN2 pin to ground (EN2 is ignored).

CHANNEL 1

BUCK

REGULATOR

(4A)

CHANNEL 2

BUCK

REGULATOR

(4A)

FB1

PVIN1

VOUT

(UP TO 8A)

VIN

EN1

EN2

COMP1

SS12

SW1

FB2

SW2

PVIN2

COMP2

VREG

Figure 39. Parallel Operation for Channel 1 and Channel 2

When operating Channel 1 and Channel 2 in the parallel

configuration, configure the channels as follows:

•

Set the input voltages and current-limit settings for

Channel 1 and Channel 2 to the same values.

•

Operate both channels in forced PWM mode.

Current balance in parallel configuration is well regulated by

the internal control loop. Figure 40 shows the typical current

balance matching in the parallel output configuration.

TOTAL OUTPUT LOAD (A)

CH1

CH2

IDEAL

Figure 40. Current Balance in Parallel Output Configuration,

VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5053include a precharged start-up

feature to protect the low-side MOSFETS from damage during

startup. If the output voltage is precharged before the regulator

is turned on, the regulator prevents the reverse inductor current,

which discharges the output capacitor, untilthe internal soft start

reference voltage exceeds the precharged voltage on the

feedback (FBx) pin.

CURRENT-LIMIT PROTECTION

The buck regulators in the ADP5053 include peak current-limit

protection circuitry tolimitthe amount ofpositivecurrentflowing

through the high-side MOSFET. The peak current limit on the

power switch limits the amount of current that can flow fromthe

input to the output. The programmable current-limit threshold

feature allows for the use of small size inductors for low current

applications.

To configure the current-limit threshold for Channel 1, connect

a resistor from the DL1 pinto ground.To configure the current-

limit threshold for Channel 2, connect another resistor from the

DL2 pin to ground. Table 10 lists the peak current-limit threshold

settings for Channel 1and Channel 2.

Table 10. Peak Current-LimitThreshold SettingsforChannel 1

and Channel 2

RILIM1 or RILIM2

Typical Peak Current-Limit Threshold (A)

Floating

4.4

47 kΩ

2.63

22 kΩ

6.44

The buck regulators in the ADP5053 include negative current-

limit protection circuitry to limit certain amounts of negative

current flowing through the low-side MOSFET.

ADP5053ACPZ-R7 数据表(PDF) 20 Page - Analog Devices

ADP5053ACPZ-R7 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载

链接网址

ADP5053ACPZ-R7 数据表(PDF) 20 Page - Analog Devices

ADP5053ACPZ-R7 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表 下载

链接网址

数据表下载