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ADP5053ACPZ-R7 数据表(PDF) 33 Page - Analog Devices

部件名 ADP5053ACPZ-R7
功能描述  Integrated Power Solution with Quad Buck
PDF  37 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5053ACPZ-R7 数据表(HTML) 33 Page - Analog Devices

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ADP5053
Data Sheet
Rev. B | Page 32 of 36
TYPICAL APPLICATION CIRCUITS
VREG
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 3
BUCK REGULATOR
(1.2A)
OSCILLATOR
INT VREG
100mA
Q1
Q2
L1
2.2µH
4.7µH
6.8µH
10µH
L2
5V REG
SYNC/MODE
RT
FB1
BST1
SW1
DL1
PGND
DL2
SW2
BST2
FB2
VREG
L3
BST3
SW3
FB3
PGND3
L4
BST4
SW4
FB4
PGND4
VREG
VREG
PVIN1
COMP1
EN1
PVIN2
EN2
PVIN3
SS34
COMP3
EN3
PVIN4
COMP4
EN4
C2
10µF
4.7nF
4.7kΩ
31.6kΩ
2.7nF
6.81kΩ
2.7nF
6.81kΩ
C1
1.0µF
C4
47µF
C3
0.1µF
C5
10µF
C6
0.1µF
C8
10µF
C9
0.1µF
C10
22µF
C11
10µF
C12
0.1µF
C13
22µF
12V
VOUT1
VOUT2
VOUT3
1.2V/2.5A
VCORE
I/O
1.5V/1.2A
4.0V TO 4.5V/1.2A
(DVS)
VOUT4
5V REG
EXPOSED PAD
SS12
C0
1.0µF
VDD
WATCHDOG
AND
RESET
WDI
VTH
ADP5053
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
C7
47µF
COMP2
4.7nF
4.7kΩ
VREG
3.3V/2.5A
VOUT1
10kΩ
10kΩ
10kΩ
SiA906EDJ
(46mΩ)
DDR
TERMINATION
LDO
DDR
MEMORY
PROCESSOR
RFPA
RF
TRANSCEIVER
RSTO
MR
Figure 52. Typical Femtocell Application, 600 kHz Switching Frequency, Fixed Output Model



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