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Data Sheet

ADP5053

Rev. B | Page 21 of 36

UNDERVOLTAGELOCKOUT (UVLO)

Undervoltage lockout circuitry monitors the input voltage levelof

each buck regulator in the ADP5053. If anyinputvoltage (PVINx

pin) falls below 3.78 V (typical), the corresponding channel is

turned off. The soft start period initiates after the input voltage

rises above 4.2 V (typical), and setting the ENx pin high enables

the corresponding channel.

Note that a UVLO condition on Channel 1 (PVIN1 pin) has

a higher priority than a UVLO condition on other channels,

which means that the PVIN1 supply must be available before

other channels become operational.

POWER-GOOD FUNCTION

The ADP5053 includes an open-drain power-good output

(PWRGD pin) that becomes active high when the selected buck

regulators are operating normally. By default, the PWRGD pin

monitors the output voltage on Channel 1. Other channels can

be configured to control the PWRGD pin when the ADP5053 is

ordered.

A logic high on the PWRGD pinindicates that theregulated output

voltage ofthe buckregulator is above 90.5% (typical) ofits nominal

output. When the regulated output voltage of the buck regulator

falls below 87.2%(typical)of its nominal output for a delaytime

greater than approximately50µs, the PWRGD pin goes low.

The output of the PWRGD pin is the logical AND of the internal

PWRGx signals. An internal PWRGx signal must be high for a

validation time of 1 ms before the PWRGD pin goes high; if one

PWRGx signal fails, the PWRGDpin goes low with no delay. The

channels that control the PWRGD pin (Channel 1 to Channel 4)

can be specified by factory fuse. The default PWRGD setting is

to monitor the output of Channel 1.

THERMAL SHUTDOWN

If the ADP5053 junction temperature exceeds 150°C,the thermal

shutdown (TSD) circuit turns off the IC except for the internal

linear regulators. Extreme junction temperatures can be the

result of high current operation,poor circuit board design, or high

ambient temperature. A 15°C hysteresis is included so that the

ADP5053 does not return to operation after thermal shutdown

until the on-chip temperature falls below 135°C. When the

device exits thermal shutdown, a soft start initiates for each

enabled channel.

SUPERVISORYCIRCUIT

The ADP5053 provides microprocessor supplyvoltage supervision

by controlling the reset input of the microprocessor. Code

execution errors are avoided duringpower-up, power-down, and

brownout conditions by asserting a reset signal when the supply

voltage is below a presetthreshold and by allowingsupplyvoltage

stabilizationwith a fixed timeoutreset pulse after the supplyvoltage

rises above the threshold.Inaddition, problems with microprocessor

code execution canbe monitored with a watchdogtimer. Note

that the supervisory circuitry activates only when one of the

ENx pins of the four buck regulators is set high.

Reset Output

The ADP5053 has an active low, open-drain reset output(RSTO).

This output requires an external pull-up resistor to connect the

reset output to a voltage rail no higher than 6 V. The resistor

must comply with the logic low and logic high voltage level

requirements of the microprocessor while also supplying input

current and leakage paths to the RSTO pin. A 10 kΩ resistor is

adequate in most situations.

The reset output asserts when the monitored rail is below the

threshold (VTH), and when WDI is not serviced within the

watchdog timeout period (tWD). The RSTO pin remains asserted

for the duration of the reset active timeout period (tRP) after VCC

rises above the reset threshold or after the watchdog timer times

out. There are four options are available for the resetactive timeout

period (tRP) via the factory fuse:1.4ms,28 ms,200 ms (default),or

1600 ms. Figure 43 illustrates the behavior of the RSTO output,

assuming that VOUT2 is selected as the rail to be monitored and it

supplies the external pull-up connected tothe RSTO output.

tRP

tRD

VOUT2

VTH

VOUT2

RSTO

Figure 43. Reset Timing Diagram

The ADP5053 has a dedicated sensinginputpin (VTH) to monitor

the supply rail. The reset threshold at the VTH input is typically

0.5 V. To monitor a voltage greater than0.5 V, connecta resistor

divider network to the device.

Do not allow the VTH input to float or to be grounded. Instead,

connect the VTH input to a supply voltage greater than its

specified threshold voltage (VTH). Add a small capacitor on the

VTH pin to improve noise rejection and false reset generation.

When monitoring the input voltage, if the selected voltage falls

below the UVLO level, the reset output (RSTO) asserts low with

the delay time (tRD). The reset output is then kept low to restart

the processor.

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