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IOBUS0 数据表(PDF) 16 Page - Future Technology Devices International Ltd.

部件名 IOBUS0
功能描述  Vinculum-II Embedded Dual USB Host Controller IC
PDF  88 Pages
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制造商  FTDI [Future Technology Devices International Ltd.]
网页  http://www.ftdichip.com
标志 FTDI - Future Technology Devices International Ltd.

IOBUS0 数据表(HTML) 16 Page - Future Technology Devices International Ltd.

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C opyright © Future T ec hnology Devic es I nternational Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
V ers ion 1 .7
Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43
3.10 Pin Configuration USB and Power
Pin No
Name
Type
Description
64 pin
48 pin
32 pin
33
25
17
USB1DP
I/O
USB host/slave port 1 - USB Data Signal Plus with
integrated pull-up/pull-down resistor.
34
26
18
USB1DM
I/O
USB host/slave port 1 - USB Data Signal Minus with
integrated pull-up/pull-down resistor.
36
28
20
USB2DP
I/O
USB host/slave port 2 - USB Data Signal Plus with
integrated pull-up/pull-down resistor.
37
29
21
USB2DM
I/O
USB host/slave port 2 - USB Data Signal Minus with
integrated pull-up/pull-down resistor.
Table 3.1 USB Interface Group
Pin No
Name
Type
Description
64 pin
48 pin
32 pin
1, 30,
35, 53
1, 24,
27, 39
1, 16,
19, 27
GND
PWR
Device ground supply pins.
2
2
2
3.3V
VREGIN
PWR
+3.3V supply to the regulator.
3
3*
3
1.8V
VCC PLL
IN
PWR
+1.8V supply to the internal clock multiplier. This pin
requires a 100nF decoupling capacitor.
* 48 pin LQFP package only – This power input is internally
connected to VREG_OUT.
All other packages need this pin connected to a 1.8V power
source. Most common applications will connect this to
VREG_OUT.
6
6
6
GND PLL
PWR
Device analogue ground supply for internal clock multiplier.
7
7*
7
VREG
OUT
Output
1.8V output from regulator to device core
* N/C on 48 pin LQFP package only.
All other packages will typically need to connect pins 7 and
3.
21, 38,
54
17, 30,
40
13, 22,
28
VCCIO
PWR
+3.3V supply to the input / output. Interface pins
(IOBUS). Leaving the VCCIO unconnected will lead to
unpredictable operation on the interface pins.
Table 3.2 Power and Ground



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