IOBUS0 datasheet(54/88 Pages) FTDI

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43

64 Pin

Package

Available

pins

48 Pin

Package

Available

pins

32 Pin

Package

Available

pins

Name

Type

Description

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

12,16,

21, 32,

36, 42,

12, 24,

spi_m_mosi

Output

Master Out Slave In

Synchronous data from master to slave

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

13, 18,

22, 33,

37, 43,

14, 25,

spi_m_miso

Input

Master In Slave Out

Synchronous data from slave to master

14, 18,

23, 27,

32, 42,

46, 50,

56, 60,

14, 19,

23, 34,

38, 44,

15, 26,

spi_m_ss_0#

Output

Active low slave select 0 from master to

slave 0

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

11, 15,

20, 31,

35, 41,

11, 23

spi_m_ss_1#

Output

Active low slave select 1 from master to

slave 1

Table 6.13 SPI Master Signal Names

The main purpose of the SPI Master block is to transfer data between an external SPI interface and the

VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus.

An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select

signal being asserted. This is followed by a data byte being clocked out with the master supplying SCLK.

The master always supplies the first byte, which is called a command byte. After this the desired number

of data bytes are transferred before the transaction is terminated by the master de -asserting slave

select.

The SPI Master will transmit on MOSI as well as receive on MISO during every data stage. At the end of

each byte spi_tx_done and spi_rx_full_int are set. Figure 6.21 Typical SPI Master Timing and

Table 6.14 SPI Master Timing show an example of this.

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