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IOBUS0 数据表(PDF) 22 Page - Future Technology Devices International Ltd.

部件名 IOBUS0
功能描述  Vinculum-II Embedded Dual USB Host Controller IC
PDF  88 Pages
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制造商  FTDI [Future Technology Devices International Ltd.]
网页  http://www.ftdichip.com
标志 FTDI - Future Technology Devices International Ltd.

IOBUS0 数据表(HTML) 22 Page - Future Technology Devices International Ltd.

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C opyright © Future T ec hnology Devic es I nternational Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
V ers ion 1 .7
Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43
4.2.4 Input / Output Multiplexer Module
VNC2 peripheral interfaces are UART, SPI slave0, SPI slave1, SPI master, FIFO-Asynchronous, FIFO-
Synchronous, GPIO, debug interface and PWM.
The I/O multiplexer allows the designer to select which peripherals are connected to the device I/O pins.
The selectable peripheral interfaces are only limited by the number of I/O pins available. All peripherals
are available across the package range except synchronous FIFO mode which cannot be selected on 32
pin packages. The available configurable I/O pins per package are as follows:
32 pin package – 12 I/O pins
48 pin package – 28 I/O pins
64 pin package – 44 I/O pins
Table 4.1 lists the peripherals which can be multiplexed to I/O and the maximum number of pins
required for each one. The designer can choose any mix of peripheral configurations as long as they are
within the specific package I/O pin count. Depending on the design not all 9 UART pins need to be
configured. Similarly the GIPO peripheral does not need all pins configured.
e.g. The 48 pin package has 28 I/O pins w hich could be configured as UART – 9 pins, SPI Master – 5
pins, FIFO Asynchronous – 12 pins and GPIO – 2 pins. This makes a total of 28 pins.
Please refer to Section 5 for a detailed description of the I/O multiplexer.
Peripherals
Maximum pins required
UART
9
SPI Slave 0
4
SPI Slave 1
4
SPI Master
5
FIFO Asynchronous
12
FIFO Synchronous
14
GPIO
40
Debug
1
PWM
8
Table 4.1 - Peripheral Pin Requirements



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