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IOBUS0 数据表(PDF) 29 Page - Future Technology Devices International Ltd. |
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IOBUS0 数据表(HTML) 29 Page - Future Technology Devices International Ltd. |
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29 / 88 page ![]() 29 C opyright © Future T ec hnology Devic es I nternational Limited Datasheet Vinculum-II Embedded Dual USB Host Controller IC V ers ion 1 .7 Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43 5.1 I/O Peripherals Signal Names Peripheral Signal Name Outputs Inputs Description Debugger debug_if 1 1 debugger interface UART uart_txd 1 0 Transmit asynchronous data output uart_rts# 1 0 Request to send control output uart_dtr# 1 0 Data acknowledge (data terminal ready control) output uart_tx_active 1 0 Enable transmit data for RS485 designs uart_rxd 0 1 Receive asynchronous data input uart_cts# 0 1 Clear to send control input uart_dsr# 0 1 Data request (data set ready control) input uart_ri# 0 1 Ring indicator control input uart_dcd# 0 1 Data carrier detect control input FIFO fifo_data 8 8 FIFO data bus fifo_txe# 1 0 When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high, then low. fifo_rxf# 1 0 When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low, then high. fifo_wr# 0 1 Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low. fifo_rd# 0 1 Enables the current FIFO data byte on D0...D7 when low. Fetches the next FIFO data byte (if available) from the receive FIFO buffer when RD# goes from high to low fifo_oe# 0 1 FIFO output enable – synchronous FIFO only fifo_clkout 0 1 FIFO clock out – synchronous FIFO only GPIO gpio 40 40 General purpose I/O SPI Slave 0 spi_s0_clk 0 1 SPI clock input – slave 0 spi_s0_ss# 0 1 SPI chip select input – slave 0 spi_s0_mosi 1 1 SPI master out serial in – slave 0 spi_s0_miso 1 0 SPI master in slave out – slave 0 SPI Slave 1 spi_s1_clk 0 1 SPI clock input – slave 1 spi_s1_ss# 0 1 SPI chip select input – slave 1 spi_s1_mosi 1 1 Master out slave in – slave 1 spi_s1_miso 1 0 Master in slave out – slave 1 SPI Master spi_m_clk 1 0 SPI clock input – master spi_m_mosi 1 1 Master out slave in - master spi_m_miso 0 1 Master in slave out - master spi_m_ss_0# 1 0 Active low slave select 0 from master to slave 0 spi_m_ss_1# 1 0 Active low slave select 1 from master to slave 1 PWM pwm 8 0 Pulse width modulation Table 5.1 I/O Peripherals Signal Names Note: # is used to indicate an active low signal. |
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