IOBUS0 datasheet(18/88 Pages) FTDI

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

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3.12 Pin Configuration Input / Output

VNC2 has multiple interfaces available for connecting to external devices. These are UART, FIFO, SPI

slave, SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins

between each peripheral.

VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the

needs of a designer. This is explained in Section 5 – I/O Multiplexer. Default configuration for each

package type is shown in Table 3.4- Default I/O Configuration. The signal names are also indicated

for the VNC1L device as it is pin-compatible with the 48 pin LQFP VNC2 device.

Note: The default values of the pins listed in the following table are only available when the

I/O Mux is enabled. A blank VNC2 chip defaults to all I/O pins as inputs.

Pin No

Name

(VINC1-L)

64 Pin

Default

48 Pin

Default

32 PIN

Default

Type

Description

IOBUS0

(BDBUS0)

debug_if

I/O

GPIO

IOBUS1

(BDBUS1)

Input

pwm[1]

gpio[A1]

I/O

GPIO

IOBUS2

(BDBUS2)

Input

pwm[2]

gpio[A2]

I/O

GPIO

IOBUS3

(BDBUS3)

Input

pwm[3]

gpio[A3]

I/O

GPIO

IOBUS4

(BDBUS4)

fifo_data[0]

spi_s0_clk

uart_txd

I/O

GPIO

IOBUS5

(BDBUS5)

fifo_data[1]

spi_s0_mosi

uart_rxd

I/O

GPIO

IOBUS6

(BDBUS6)

fifo_data[2]

spi_s0_miso

uart_rts#

I/O

GPIO

IOBUS7

(BDBUS7)

fifo_data[3]

spi_s0_ss#

uart_cts#

I/O

GPIO

IOBUS8

(BCBUS0)

fifo_data[4]

spi_m_clk

spi_s0_clk

I/O

GPIO

IOBUS9

(BC BUS1)

fifo_data[5]

spi_m_mosi

spi_s0_mosi

I/O

GPIO

IOBUS10

(BCBUS2)

fifo_data[6]

spi_m_miso

spi_s0_miso

I/O

GPIO

IOBUS11

(BCBUS3)

fifo_data[7]

spi_m_ss_0#

spi_s0_ss#

I/O

GPIO

IOBUS12

(ADBUS0)

fifo_rxf#

uart_txd

I/O

GPIO

IOBUS13

(ADBUS1)

fifo_txe#

uart_rxd

I/O

GPIO

IOBUS14

(ADBUS2)

fifo_rd#

uart_rts#

I/O

GPIO

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