IOBUS0 datasheet(64/88 Pages) FTDI

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43



Generation of up to 4-pulse signal with controlled output enable and configurable initial state



Interrupt

A single PWM cycle can have up to 4 pulses (8 edges). The PWM block uses a 16-bit counter to

determine the period of a single PWM cycle. This counter counts system clocks which can also be divided

by an optional 8-bit prescaler. The PWM drivers allow the user to select when PWM output toggles. These

values correspond to the values of 16-bit counter. For example, on the timing diagram below - Figure

6.24, the 16-bit counter counts to 23 and pwm_out[0] output toggles when the counter’s current value is

equal to 7, 8, 12, 14, 15, 16, 19 and 22.

Figure 6.24 PWM – Timing Diagram

The user can also select the initial state of each of the PWM outputs (HI or LOW). PWM outputs can also

be enabled continuously or a cycle can be repeated 1..255 times. The PWM cycle can be started by the

PWM driver or externally using a trigger input.

6.10 General Purpose Input Output

VNC2 provides up to 40 configurable Input/output pins depending on the package. The Input/output pins

are connected to Ports A through E. These ports are controlled by the VNC2 CPU. All ports are

configurable to be either inputs or outputs and allow level or edge driven interrupts to be generated.

To simplify the use of the 40 available GPIO signals, they have been grouped into 5 "ports", identified as

A, B, C, D and E. Each port is 1 byte wide and the RTOS drivers will a llow each port to be individually

accessed.

Each GPIO signal is mapped on to a bit of the port value. For example, gpio[A0] is the least significant

bit of the value read from or written to GPIO port A. Similarly, gpio[A7] is the most significant bit of the

value read from or written to GPIO port A (see Figure 6.25 GPIO Port Groups)

Each pin can be individually configured as input or output. GPIO port A supports an interrupt that can be

used to detect a state change of any of its 8 pins. Port B features a more sophisticated set of 4

configurable interrupts that can be associated with individual pins and supports several conditions such

as positive edge, negative edge, high or low.

PORT A

gpio[A0]

gpio[A1]

gpio[A2]

gpio[A3]

gpio[A4]

gpio[A5]

gpio[A7]

gpio[A6]

PORT B

gpio[B0]

gpio[B1]

gpio[B2]

gpio[B3]

gpio[B4]

gpio[B5]

gpio[B7]

gpio[B6]

PORT C

gpio[C0]

gpio[C1]

gpio[C2]

gpio[C3]

gpio[C4]

gpio[C5]

gpio[C7]

gpio[C6]

PORT D

gpio[D0]

gpio[D1]

gpio[D2]

gpio[D3]

gpio[D4]

gpio[D5]

gpio[D7]

gpio[D6]

PORT E

gpio[E0]

gpio[E1]

gpio[E2]

gpio[E3]

gpio[E4]

gpio[E5]

gpio[E7]

gpio[E6]

Figure 6.25 GPIO Port Groups

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