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IOBUS0 数据表(PDF) 62 Page - Future Technology Devices International Ltd. |
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IOBUS0 数据表(HTML) 62 Page - Future Technology Devices International Ltd. |
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62 / 88 page ![]() 62 C opyright © Future T ec hnology Devic es I nternational Limited Datasheet Vinculum-II Embedded Dual USB Host Controller IC V ers ion 1 .7 Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43 6.7.1 Read / Write Transaction Synchronous FIFO Mode When in Synchronous FIFO interface mode, the timing of read and write operations on the FIFO interface are shown in Figure 6.23 Synchronous FIFO mode Read / Write Cycle and Table 6.19 Synchronous FIFO mode Read / Write Timing In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An external device synchronises to the CLKOUT output and it also has access to the output enable OE# input to control data flow. An external device should drive output enable OE# low before pulling RD# line down. When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when there is still data to be read. Similarly when bursts of data are to be written to the module WR# should be kept low. TXE# remains low when there is still space available for the data to be written. Figure 6.23 Synchronous FIFO mode Read / Write Cycle |
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