TNETX15AE datasheet(36/78 Pages) TI

36 / 78 page

TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

TNETX15AE DRAM and EAM interface (continued)

The TNETX15AE must determine that the data being written to memory is the first buffer of a data frame and

not an IOB index buffer. The buffer contains packet data if the IOB bit is 0. The channel/source port code is

latched

from

bits

DD27–DD24

during

the

forward

pointer

(FPTR)

transfer

when

TNETX3150/TNETX3150A/TNETX3100 is writing packet data to DRAM.

The TNETX15AE must determine the start of frame by looking at the flag in cycle 1. The flag is given in the

DD35–DD32 terminals. The SOF is shown in the following table in cycle 1 at bit (35–34) = 01b.

CYCLE

BIT

CYCLE

IOB

Parity†

Tag†

Channel code

Forward pointer†

Reserved

Most-significant 32 bits of DA

Channel code†

Most-significant 16 bits SA

Least-significant 16 bits DA

Reserved

Least-significant 32 bits of SA

•

Flags†

Data†

N–1

EOB

Valid bytes†

Data†

EOF

Frame status†

CRC

† These bits are ignored by the TNETX15AE.

The TNETX15AE destination lookup cycle begins when it latches the partial destination address to begin the

table lookup in cycle 1, and ends when it outputs an EAM code within the allocated 440 ns after the SOF

condition is met. It must pick up the 16 bits at the destination in cycle 2 to complete the decode.

The channel-code field in the body of the frame is exactly the same as that in the forward pointer. The

TNETX15AE uses the channel code from the forward pointer.

decoding the destination address (DA) and source address (SA) from the DRAM bus

The TNETX3150/TNETX3150A/TNETX3100 writes data to the DRAM buffers in a specific format (refer to the

TNETX3150/TNETX3150A/TNETX3100 data sheet for additional information on this format). The TNETX15AE

recognizes this format to determine the correct destination and source addresses. The format for the DA and

the SA is shown in the following:

CYCLE

BIT

CYCLE

DA23–DA16

DA31–DA24

DA39–32

DA47–DA40

SA39–SA32

SA47–SA40

DA7–DA0

DA15–DA8

SA7–SA0

SA15–SA8

SA23–SA16

SA31–SA24

The TNETX15AE will latch and save the source address, cycles 2 and 3, if it is not already saving one. A

source-address lookup will take place when there is no activity (TNETX3150/TNETX3150A/TNETX3100 to

DRAM), when the transfer to memory is not the first 64 bytes of a packet, or when the transfer is from memory

to an output FIFO.

TNETX15AE 数据表(PDF) 36 Page - Texas Instruments

TNETX15AE 数据表(HTML) 36 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

数据表下载

链接网址

TNETX15AE 数据表(PDF) 36 Page - Texas Instruments

TNETX15AE 数据表(HTML) 36 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

数据表 下载

链接网址

数据表下载