TNETX15AE datasheet(61/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

masking interrupts

The TNETX15AE can mask interrupts. This is accomplished by an interrupt masking register (intmask). The

int and intmask registers have a one-to-one correspondence. The only way EINT is asserted is if both the

corresponding bits in the int and intmask are in a 1 state. The logic for the interrupt masking is shown in

Figure 17.

Int

Intmask

Interrupt Mask Register

Interrupt Register

AND

EINT

Figure 17. Interrupt Masking Logic

test interrupts (INT)

Test interrupts are generated by asserting the INT bit in the int register. The INT bit in the intmask register also

must be set to a 1 state for the interrupt to take effect. The INT bit is used to give the programmer an easy way

to test interrupt detection. This bit is the only bit in the int register that is writeable.

ADD interrupts (NEW, NEWM, CHNG, CHNGM, SECVIO, SECVIOM, and FULL)

The ADD interrupts generate collateral information in the following registers:

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO

ADDRESS

Newnode23–Newnode16

Newnode31–Newnode24

Newnode39–Newnode32

Newnode47–Newnode40

0x30

Newport

Newnode7–Newnode0

Newnode15–Newnode8

0x34

ADD interrupts are sourced by the ADD logic operation based on information from the wire. ADD indicates a

new address by a NEW interrupt, an address is on a new port by a CHNG interrupt, and a security violation by

a SECVIO interrupt.

The FULL interrupt indicates that ADD needed to start AGE (to free up table space) if NAUTO is 0, or the host

needs to delete some addresses if NAUTO = 1.

The FULL interrupt indicated that table resources are exhausted to the point where (wire or DIO) ADD cannot

take place. If NAUTO = 0, AGE will delete oldest entries when another ADD is requested. IF NAUTO = 1, the

host must do some deletes before the next DIO ADD can complete.

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