TNETX15AE datasheet(62/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

ADD interrupts (NEW, NEWM, CHNG, CHNGM, SECVIO, SECVIOM, and FULL) (continued)

The add interrupts are indicated in the interrupt register and the information for the particular interrupt is placed

in the newnode and newport registers. Since there is only one set of registers that is shared for these interrupts,

and to ensure that the information placed in these registers is not corrupted during reads, ADD locks the

newnode and newport registers until the most-significant byte of newport is read.

Locking these registers means that ADD does not have a place to put information for new events. If additional

events are missed, they are indicated in the int register as missed interrupts (NEWM, CHNGM, and SECVIOM).

On a NEW interrupt, the newport register contains information about the port for the new address. On a CHNG

interrupt, this register identifies the new port address. On a SECVIO interrupt, the address does not move to

the port, but the newport register indicates the port to which it tried to move.

aging interrupts (AGE, AGEM)

When an address is aged out by the internal AGE logic, it generates an interrupt and reports about that address

in the following registers:

BYTE 3

BYTE 2

BYTE 1

BYTE 0

DIO

ADDRESS

Agednode23–Agednode16

Agednode31–Agednode24

Agednode39–Agednode32

Agednode47–Agednode40

0x40

Agedport

Agednode7–Agednode0

Agednode15–Agednode8

0x44

AGE indicates an interrupt every time that it ages out a node. It places the information on the node (being aged

out) on the agednode register, the node’s port on agedport. These registers are locked when a new interrupt

is given to protect the information contained.

Missed interrupts due to these registers being locked are indicated as an AGEM interrupt. These registers are

unlocked when the agedport register is read.

statistic interrupt (STAT)

The statistic interrupt is given when one of the statistic registers (except for numnodes) becomes one-half full;

the most-significant bit becomes a 1. This is an indication to the management CPU that the statistic registers

should be read to avoid counter overrun. Reading the most-significant byte of a statistic counter, except for

numnodes, clears it. The host should read least-significant byte, then most-significant byte, and be prepared

for a carry between byte reads.

If a carry took place between byte needs, the statistic count will appear to have jumped by 255 instead of one

count.

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